Re: [PATCH v5 1/2] dt-bindings: clock: qcom: Add LPASS VA CSR HeartBeat pulse clock

On Thu, Aug 06, 2026 at 08:21:36PM +0530, Sarath Ganapathiraju via B4 Relay wrote:
> From: Sarath Ganapathiraju <[email protected]>
> 
> Add a binding for the Qualcomm LPASS VA CSR rate generator node that
> exposes the lpass_heartbeat_pulse clock on hawi.

Hawi is a proper noun, so it should always be written with capital 'H'.

> 
> The HeartBeat Pulse (also known as RateGen Pulse) synchronizes the
> start of the DMAs and Codec Interfaces for the audio usecase and can
> serve as a periodic wakeup source for the DSP.
> 
> Signed-off-by: Sarath Ganapathiraju <[email protected]>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> ---
>  .../bindings/clock/qcom,hawi-lpass-va-csr.yaml     | 51 ++++++++++++++++++++++
>  1 file changed, 51 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/qcom,hawi-lpass-va-csr.yaml b/Documentation/devicetree/bindings/clock/qcom,hawi-lpass-va-csr.yaml
> new file mode 100644
> index 000000000000..9935173d8bee
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,hawi-lpass-va-csr.yaml
> @@ -0,0 +1,51 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,hawi-lpass-va-csr.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm LPASS VA CSR heartbeat pulse clock provider
> +
> +maintainers:
> +  - Srinivas Kandagatla <[email protected]>
> +  - Sarath Ganapathiraju <[email protected]>
> +
> +description:
> +  The LPASS (Low Power Audio Subsystem) VA CSR block contains a rate
> +  generator that produces a periodic HeartBeat Pulse, also known as
> +  the RateGen Pulse. This pulse synchronizes the start of DMAs and
> +  Codec Interfaces for audio usecases and can serve as a periodic
> +  wakeup source for the DSP.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - qcom,hawi-lpass-va-csr
> +
> +  reg:
> +    maxItems: 1
> +    description: Address and size of the rate generator registers within
> +      the VA CSR block.
> +
> +  "#clock-cells":
> +    const: 0
> +
> +required:
> +  - compatible
> +  - reg
> +  - "#clock-cells"
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    soc {
> +      #address-cells = <2>;
> +      #size-cells = <2>;
> +
> +      clock-controller@7eed000 {
> +        compatible = "qcom,hawi-lpass-va-csr";
> +        reg = <0x0 0x07eed000 0x0 0x14>;

The two 0x0 cells are just there in the normal dtsi because we need
address- and size-cells of 2. But you don't need that in your example.

If you change this to <0x07eed000 0x14> you can drop the
address/size-cells and the whole soc {} level from the example.


That said, is this really a 20 byte large IP-block? Or is this part of
some larger function? Will we have overlapping/conflicting mappings of
this block?

Regards,
Bjorn

> +        #clock-cells = <0>;
> +      };
> +    };
> 
> -- 
> 2.34.1
> 
>