Re: [PATCH v2 03/12] clk: divider: Introduce CLK_DIVIDER_EVEN_INTEGERS_NO_OFFSET flag

Hi Luo,

On Thu, Aug 06, 2026 at 11:53:07PM -0700, Luo Jie wrote:
> Some hardware dividers derive an even divisor directly from the raw
> register value, i.e. divisor = 2 * val, with no +1 offset. This differs
> from CLK_DIVIDER_EVEN_INTEGERS, which is one-based (divisor = 2 *
> (val + 1)).
> 
> Add CLK_DIVIDER_EVEN_INTEGERS_NO_OFFSET for this variant, updating
> _get_maxdiv()/_get_div()/_get_val() accordingly. _is_valid_div() is
> extended to also reject odd divisors, since _get_val()'s `div >> 1`
> would otherwise silently decode them to the wrong even value (e.g. 3
> -> 1 -> 2).
> 
> To avoid regressing rate requests that previously computed an odd
> divisor (which used to succeed with a silently wrong rate), round to
> the nearest even divisor in _div_round_up(), _div_round_closest(), and
> _next_div(), mirroring how CLK_DIVIDER_POWER_OF_TWO already rounds to
> the nearest power of two.
> 
> Also guard divider_ro_determine_rate() against a zero divisor, which
> can occur from an unprogrammed/reset register, the same way
> divider_recalc_rate() already does: WARN unless CLK_DIVIDER_ALLOW_ZERO
> is set, and return -EINVAL.
> 
> Signed-off-by: Luo Jie <[email protected]>

One of the other patches in your series says:

    The NSS (network subsystem) clock is derived from the CMN PLL output
    divided by 2 and then further divided by a configurable 6-bit divider.

Can you register a fixed-factor-clock parent with /2, then use
CLK_DIVIDER_ONE_BASED? That should yield the same results and it may
more accurately represent the hardware as well.

Brian