Re: [PATCH v3 4/6] arm64: dts: intel: agilex5: add USB3.1 controller node

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Devicetree structurally contradicts itself regarding 40-bit DMA support for the USB3.1 controller.
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--- Patch [4]: [PATCH v3 4/6] arm64: dts: intel: agilex5: add USB3.1 controller node ---
commit 2f2039b2059cdc372b94f8f6d45151844510ff80
Author: Adrian Ng Ho Yin <[email protected]>

arm64: dts: intel: agilex5: add USB3.1 controller node

This patch adds a DTS node for the Synopsys DWC3 USB3.1 controller on the
Agilex5 SoC. It places the device under a simple-bus configured with a 40-bit
DMA window and enables it in host mode on the SoCDK board.

> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> index b06c6d5d60eed..043b980832c23 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> @@ -494,6 +494,33 @@ usb0: usb@10b00000 {
>  			status = "disabled";
>  		};
>  
> +		usb31_bus: usb-bus@11000000 {
> +			compatible = "simple-bus";
> +			#address-cells = <1>;
> +			#size-cells = <2>;
> +			ranges = <0x00 0x11000000 0x00 0x100000>;
> +			dma-ranges = <0x00 0x00 0x100 0x00>;

[Severity: High]
Does this dma-ranges property structurally contradict the #address-cells
configuration for a 40-bit DMA window?

The usb31_bus node and its parent soc@0 both use #address-cells = <1>.
With a 32-bit (4 GB) child address space, is it mathematically possible to
accommodate the 1 TB (<0x100 0x00>) window length specified in dma-ranges?

When the Linux OF core parses this, won't it truncate the window against the
parent's 32-bit boundaries and silently limit the device to 32-bit DMA?

[ ... ]

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Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=4