[PATCH v4 2/7] arm64: dts: renesas: r9a09g077: Adjust CPG register region sizes
Prabhakar <[email protected]>
| Newsgroups | org.kernel.vger.linux-clk,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel,org.kernel.vger.linux-renesas-soc,org.kernel.vger.linux-watchdog |
|---|---|
| Message-ID | <[email protected]> |
From: Lad Prabhakar <[email protected]> Increase the size of both CPG register regions from 64 KiB to 128 KiB. On the RZ/T2H SoC, the CPG/MSSR block is a multi-function block where, apart from clock and reset handling, it supports other features including clock monitoring, write protection, and peripheral configuration registers. Expand the mapped register regions to cover the entire register space of this block so these additional features can be utilized. Signed-off-by: Lad Prabhakar <[email protected]> --- v3->v4: - No change v2->v3: - new patch --- arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi index 33f953c110bb..de20bed2797b 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -1075,8 +1075,8 @@ xspi1: spi@801c1000 { cpg: clock-controller@80280000 { compatible = "renesas,r9a09g077-cpg-mssr"; - reg = <0 0x80280000 0 0x10000>, - <0 0x81280000 0 0x10000>; + reg = <0 0x80280000 0 0x20000>, + <0 0x81280000 0 0x20000>; clocks = <&extal_clk>; clock-names = "extal"; #clock-cells = <2>; -- 2.43.0