Re: [PATCH v2 08/16] clk: qcom: gcc-qcs615: Tie the CX power domain to controller

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Unclocked register access during reset assertion because qcom_reset_ops do not wake the device from RPM suspend.
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--- Patch [8]: [PATCH v2 08/16] clk: qcom: gcc-qcs615: Tie the CX power domain to controller ---
commit c06f319be5cd4791e28ad1c311d665bbd4af3230
Author: Abel Vesa <[email protected]>

clk: qcom: gcc-qcs615: Tie the CX power domain to controller
    
Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

> diff --git a/drivers/clk/qcom/gcc-qcs615.c b/drivers/clk/qcom/gcc-qcs615.c
> index 57f8c80c6f324..601c81c844505 100644
> --- a/drivers/clk/qcom/gcc-qcs615.c
> +++ b/drivers/clk/qcom/gcc-qcs615.c
> @@ -2967,6 +2967,7 @@ static const struct qcom_cc_desc gcc_qcs615_desc = {
>  	.resets = gcc_qcs615_resets,
>  	.num_resets = ARRAY_SIZE(gcc_qcs615_resets),
>  	.gdscs = gcc_qcs615_gdscs,
> +	.use_rpm = true,

[Severity: High]
Will enabling runtime PM here cause unclocked register accesses during reset 
assertions?

When use_rpm is set to true, the GCC controller can be runtime suspended. If a 
consumer device driver calls reset_control_assert() before enabling its clocks, 
the underlying reset callback executes a register write without first waking up 
the GCC device.

Looking at the qcom reset operations:

drivers/clk/qcom/reset.c:qcom_reset_set_assert() {
    ...
    regmap_update_bits(rst->regmap, map->reg, mask, assert ? mask : 0);

    /* Read back the register to ensure write completion, ignore the value */
    regmap_read(rst->regmap, map->reg, &mask);
    ...
}

Since there is no pm_runtime_resume_and_get() or similar mechanism to wake the 
controller before the regmap_update_bits() call, will this write to a powered-off 
MMIO space and trigger a synchronous external abort?

>  	.num_gdscs = ARRAY_SIZE(gcc_qcs615_gdscs),
>  };

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Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=8