Re: [PATCH] clk: qcom: ipq-cmn-pll: keep the CMN block bus clocks enabled

On Thu, Aug 20, 2026 at 01:39:52PM +0800, Jie Luo wrote:
> The CMN PLL output clocks do not depend on the AHB or SYS clocks. They
> continue to operate correctly at the fixed rates even when the AHB
> and SYS clocks are disabled.

The PLL outputs keep running, but the AHB register interface does not.
Once autosuspend gates AHB/SYS, any later register access to the CMN
block hangs the bus. That is the bug we are fixing.

> On IPQ5018, the CMN PLL provides a 50 MHz output clock that is used as
> the reference clock for the connected Ethernet device.

Correct, and that consumer is hardwired in silicon — the internal GE
PHY and uniphy blocks take proxied this clock without any Linux driver
calling clk_get() on it. Therefore no device link exists to keep the
provider active, and CCF rightfully gates the bus clocks after probe.

Adding DT consumers would require touching PHY and datapath drivers
across multiple subsystems just to create artificial clk references.
That is not a stable material. The v4 driver fix is minimal, correct,
and self-contained.

Reviewed-by: Mieczyslaw Nalewaj <[email protected]>