[PATCH v2 2/2] arm64: dts: qcom: hamoa: Add ICE node for UFS inline encryption
Wenjia Zhang <[email protected]>
| Newsgroups | org.kernel.vger.linux-crypto,org.kernel.vger.linux-arm-msm,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel |
|---|---|
| Message-ID | <[email protected]> |
Add the Inline Crypto Engine (ICE) device node to describe the hardware-accelerated inline encryption for UFS storage on the Hamoa IoT EVK board (Qualcomm X1E80100 SoC). Signed-off-by: Wenjia Zhang <[email protected]> --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index 0840eb2f884f98d76442fac7888ed49a07780898..0c9b459055d720a528a319272161d1d7446daefd 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -4176,6 +4176,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, phys = <&ufs_mem_phy>; phy-names = "ufsphy"; + qcom,ice = <&ice>; + #reset-cells = <1>; status = "disabled"; @@ -4221,6 +4223,17 @@ opp-300000000 { }; }; + ice: crypto@1d88000 { + compatible = "qcom,x1e80100-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0x0 0x01d88000 0x0 0x18000>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc GCC_UFS_PHY_GDSC>; + }; + cryptobam: dma-controller@1dc4000 { compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; reg = <0x0 0x01dc4000 0x0 0x28000>; -- 2.43.0