Re: [PATCH v3 1/3] perf/cxlpmu: Fix 64-bit write to 32-bit HDM filter register
Richard Cheng <[email protected]>
| Newsgroups | org.kernel.vger.linux-cxl,org.kernel.vger.linux-perf-users |
|---|---|
| Message-ID | <alXZx8VlmC5RRofg@MWDK4CY14F> |
On Sun, Jul 12, 2026 at 11:11:10PM +0800, Davidlohr Bueso wrote:
> The HDM decoder filter configuration register is 32 bits wide, but the
> driver programs it with a 64-bit writeq(). The upper half of the write
> is always zero and lands in the adjacent Filter ID 1 (Channel/Rank/Bank)
> configuration register at offset+4.
>
> Fixes: 5d7107c72796 ("perf: CXL Performance Monitoring Unit driver")
> Signed-off-by: Davidlohr Bueso <[email protected]>
> ---
> drivers/perf/cxl_pmu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/perf/cxl_pmu.c b/drivers/perf/cxl_pmu.c
> index 68a54d97d2a8..39b46550a510 100644
> --- a/drivers/perf/cxl_pmu.c
> +++ b/drivers/perf/cxl_pmu.c
> @@ -635,7 +635,7 @@ static void cxl_pmu_event_start(struct perf_event *event, int flags)
> cfg = cxl_pmu_config2_get_hdm_decoder(event);
> else
> cfg = GENMASK(31, 0); /* No filtering if 0xFFFF_FFFF */
> - writeq(cfg, base + CXL_PMU_FILTER_CFG_REG(hwc->idx, 0));
> + writel(cfg, base + CXL_PMU_FILTER_CFG_REG(hwc->idx, 0));
> }
>
> cfg = readq(base + CXL_PMU_COUNTER_CFG_REG(hwc->idx));
> --
> 2.39.5
>
Reviewed-by: Richard Cheng <[email protected]>