Re: [PATCH v3 3/3] perf/cxlpmu: Support Channel/Rank/Bank filter

On Tue, 14 Jul 2026, Richard Cheng wrote:

>On Sun, Jul 12, 2026 at 11:11:12PM +0800, Davidlohr Bueso wrote:
>> @@ -621,6 +646,32 @@ static int cxl_pmu_event_init(struct perf_event *event)
>>		return -EOPNOTSUPP;
>>	/* TODO: Validation of any filter */
>>
>> +	if (cxl_pmu_config1_crb_filter_en(event)) {
>> +		if (!info->filter_crb)
>> +			return -EINVAL;
>> +		/*
>> +		 * CRB filtering (Filter ID 1) is only valid for the DDR
>> +		 * Interface, Queue Occupancy, Queue Residency and Retry
>> +		 * event groups (CXL 4.0 Table 13-5).
>> +		 */
>> +		switch (cxl_pmu_config_get_gid(event)) {
>> +		case CXL_PMU_GID_DDR:
>> +		case CXL_PMU_GID_QUEUE_OCC:
>
>Should we also validate the Event Vendor ID?
>
>GID namespace is scoped by the Vendor ID, while the groups listed
>in CXL 4.0 Table 13-5 are under CXL vendor ID.
>A vendor-specific event could reuse one of these numeric GID and pass
>this switch even though the CXL CRB rules don't apply to it.
>
>I would suggest to reject non-CXL events before the switch
>"""
>if (cxl_pmu_config_get_vid(event) != PCI_VENDOR_ID_CXL)
>    return -EINVAL;
>"""
>
>Do you think this make sense to you?

Good catch, yes this makes sense.

Thanks,
Davidlohr