Re: [PATCH v18 10/13] cxl: Add port and dport identifiers to CXL AER trace events
Jonathan Cameron <[email protected]>
| Newsgroups | org.kernel.vger.linux-cxl,dev.linux.lists.sashiko-reviews,org.kernel.vger.linux-pci |
|---|---|
| Message-ID | <20260721005312.3c0bb10e@jic23-huawei> |
On Mon, 20 Jul 2026 10:14:27 -0500 "Bowman, Terry" <[email protected]> wrote: > On 7/17/2026 5:53 PM, [email protected] wrote: > > Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider: > > - [High] Asynchronous CPER error handling races with ACPI driver unbind, causing Use-After-Free of cxl_dport. > This is a false positive. > > The Downstream port lifecycle is tied to the Port's xarray and synchronized here using the > Port's device lock. > > > - [High] Live PCI configuration space reads on a potentially frozen or dead link during AER recovery. > This is fixed in patch 11 with introduction of cached PCI DSN. Why not flip the patch order?