Re: [PATCH v10 03/12] cxl: Share HDM decoder decode logic
[email protected] Tue, 04 Aug 2026 19:45:28 +0000
| Newsgroups | org.kernel.vger.linux-cxl,org.kernel.vger.linux-pci |
|---|---|
| Message-ID | <[email protected]> |
> Add a helper to resolve a CXL port upstream PCI device for paths > that need to associate CXL core state with the parent PCI function. >=20 > Move HDM decoder register decoding into a helper shared by normal CXL > core enumeration and early PCI HDM cache setup. This keeps validation of > base, size, interleave, target type, and enable state in one place before > adding another HDM parser. >=20 > Signed-off-by: Srirangan Madhavan <[email protected]> Sashiko has reviewed this patch and found no issues. It looks great! --=20 Sashiko AI review =C2=B7 https://sashiko.dev/#/patchset/20260804192958.1823= [email protected]?part=3D3