Re: [PATCH v10 12/12] PCI/CXL: Restore HDM state after CXL bus reset

Thank you for your contribution! Sashiko AI review found 1 potential issue(=
s) to consider:

Pre-existing issues:
- [High] cxl_bus reset method is bypassed by standard bus reset if SBR is u=
nmasked, silently dropping HDM state.
--

--- Patch [12]: [PATCH v10 12/12] PCI/CXL: Restore HDM state after CXL bus =
reset ---
commit 40f2649e2ecc899dc17ea040e81eb83bfd2d204c
Author: Srirangan Madhavan <[email protected]>

PCI/CXL: Restore HDM state after CXL bus reset

The commit attempts to restore CXL HDM decoder state after a successful CXL
bus reset while the IOMMU reset block is active. It restores PCI config
state first so BARs are valid before HDM MMIO access. It also adds a check
to reject CXL bus reset for multifunction devices.

> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index ef25ba5f7fe95..7d1e968a2aa2d 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c

[ ... ]

> @@ -5004,6 +5007,9 @@ static int cxl_reset_bus_function(struct pci_dev *d=
ev, bool probe)
>  		pci_write_config_word(bridge, dvsec + PCI_DVSEC_CXL_PORT_CTL,
>  				      reg);
> =20
> +	if (!rc)
> +		rc =3D cxl_restore_hdm_after_pci_reset(dev);
> +
[Severity: High]
This isn't a bug introduced by this patch, but is there a situation where
cxl_reset_bus_function() is bypassed by the standard bus reset?

Looking at the pci_reset_fn_methods array in drivers/pci/pci.c:

const struct pci_reset_fn_method pci_reset_fn_methods[] =3D {
	...
	{ pci_pm_reset, .name =3D "pm" },
	{ pci_reset_bus_function, .name =3D "bus" },
	{ cxl_reset_bus_function, .name =3D "cxl_bus" },
};

The standard "bus" reset precedes the "cxl_bus" reset.

If a CXL device has its Secondary Bus Reset (SBR) unmasked, will the
standard bus reset probe successfully and handle the reset instead?

If so, does this cause the new cxl_restore_hdm_after_pci_reset() logic to
be silently skipped during a PCI reset (e.g., from VFIO or sysfs)?

Could this result in the CXL HDM decoder state being wiped without getting
restored, potentially breaking CXL memory access and leading to Machine
Check Exceptions?

>  	pci_dev_reset_iommu_done(dev);
>  	return rc;
>  }

--=20
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