Re: [PATCH v5 2/4] cxl/hdm: Make switch decoder target parsing endian-safe
Li Ming <[email protected]>
| Newsgroups | org.kernel.vger.linux-cxl |
|---|---|
| Message-ID | <[email protected]> |
On 8/8/2026 8:05 AM, Alison Schofield wrote:
> Switch decoder target IDs are stored one per byte, starting with
> target 0 in the least significant byte. The current code accesses
> those bytes in memory order, which only matches register order on
> little-endian hosts.
>
> On big-endian hosts, the target IDs are reversed and the decoder is
> associated with the wrong downstream ports.
>
> Place the register values in a byte array in little-endian order and
> index the target IDs from there, so the target mapping is independent
> of host endianness.
>
> Fixes: d17d0540a0db ("cxl/core/hdm: Add CXL standard decoder enumeration to the core")
> Signed-off-by: Alison Schofield <[email protected]>
Reviewed-by: Li Ming <[email protected]>