Re: [PATCH v7 1/8] cxl: Add BI register probing and port initialization

On Fri, 07 Aug 2026, Richard Cheng wrote:

>On Tue, Jul 28, 2026 at 07:41:29AM +0800, Davidlohr Bueso wrote:
>> +static void cxl_port_map_bi(struct cxl_port *port)
>> +{
>> +	struct cxl_register_map *map = &port->reg_map;
>> +	struct cxl_dport *parent_dport = port->parent_dport;
>> +	struct device *udev;
>> +	int cap_id;
>> +
>> +	/* no upstream BI registers above host bridges or the cxl_root */
>> +	if (!parent_dport || is_cxl_root(parent_dport->port))
>> +		return;
>> +
>> +	udev = is_cxl_endpoint(port) ?
>> +		port->uport_dev->parent : port->uport_dev;
>> +	if (!dev_is_pci(udev))
>> +		return;
>> +
>> +	/* BI requires 256B Flit on the upstream link */
>> +	if (!cxl_pci_flit_256(to_pci_dev(udev)))
>> +		return;
>> +
>> +	/* map this port's own BI capability */
>> +	if (is_cxl_endpoint(port)) {
>> +		if (!map->component_map.bi_decoder.valid) {
>> +			dev_dbg(&port->dev, "BI Decoder registers not found\n");
>> +			return;
>> +		}
>> +		cap_id = CXL_CM_CAP_CAP_ID_BI_DECODER;
>> +	} else {
>> +		if (!map->component_map.bi_rt.valid) {
>> +			dev_dbg(&port->dev, "BI RT registers not found\n");
>> +			return;
>> +		}
>> +		cap_id = CXL_CM_CAP_CAP_ID_BI_RT;
>> +	}
>> +
>> +	map->host = &port->dev;
>> +	if (cxl_map_component_regs(map, &port->regs, BIT(cap_id)))
>> +		dev_dbg(&port->dev, "Failed to map BI capability 0x%x\n",
>> +			cap_id);
>
>Do we need to distinguish an optional absent BI RT from an advertised BI RT
>that failed to map?
>
>In both cases port->regs.bi_rt is NULL, then cxl_is_bi_capable() accepts a NULL BI
>pointer for a USP, and __cxl_bi_ctrl_dport() consequently skips __cxl_bi_commit_rt().
>
>So a mapping failure of a present BI RT can be treated like the switch do not need a
>route table.
>
>I think we should treat mapping failure of BI RT differently.

I agree. For example a switch that requires an explicit BI RT commit would have BI
enabled below it without its route table ever being committed. I have fixed this
for v8 such that cxl_is_bi_capable() does:

	if (port_iter->reg_map.component_map.bi_rt.valid &&
	    !port_iter->regs.bi_rt) {
		dev_dbg(cxlds->dev,
			"BI RT advertised but unmapped\n");
		return;
	}

So then the later cxl_bi_setup will fail.

Thanks,
Davidlohr