Re: [PATCH net-next v5 0/3] Add DAPU Telecom DAP8211R(I) Gigabit Ethernet PHY driver

Hi Andrew,

On Tue, Aug 4, 2026 at 4:32 PM Andrew Lunn <[email protected]> wrote:
> That is a very odd setup, half the 2ns delay the RGMII standard asks
> for? Do you have an explanation for this?
I think this is a poor example, as the delay is due to clock inversion
due to a mismatch in the PCB parameters.
Perhaps I should use a more standard delay as an example as <1950>.

> Have you verified the writing of the delays in the PHY register don't
> have a 1 bit shift error?

I verified them by reading back the RGMII_CON register (0xA003) after
configuration,
and the values are being applied correctly with no bit-shift error.
Just my failed in example value =)

Thank you for your time and review.

--
Best regards,
Artem