Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
New issues:
- [Low] The newly introduced `AIROHA_PINCTRL_GPIO` macro is completely unused.
Pre-existing issues:
- [High] The patch fixes the pcie_reset pin muxing for EN7581 by clearing the mask in REG_GPIO_PON_MODE, but fails to apply the identical fix to AN7583.
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--- Patch [6]: [PATCH v9 06/36] pinctrl: airoha: an7581: fix mux/conf of pcie_reset pins ---
commit c635409b9a1090e964e56f47b67fd7f0f0235294
Author: Mikhail Kshevetskiy <[email protected]>
pinctrl: airoha: an7581: fix mux/conf of pcie_reset pins
This commit fixes the pinmux configuration for pcie_reset pins on the EN7581
SoC by mapping them to the correct pins (60-62) and updating their muxing
logic to allow proper configuration as PCIe reset, GPIO, or PWM pins. It also
introduces new GPIO and PWM macros to handle the corrected pin functionalities.
> diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
> --- a/drivers/pinctrl/airoha/pinctrl-airoha.c
> +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
> @@ -1406,6 +1414,45 @@ static const struct airoha_pinctrl_func_group pnand_func_group[] = {
> },
> };
>
> +#define AIROHA_PINCTRL_GPIO(gpio, mux_val) \
> + { \
> + .name = (gpio), \
> + .regmap[0] = { \
> + AIROHA_FUNC_MUX, \
> + REG_GPIO_PON_MODE, \
> + (mux_val), \
> + (mux_val) \
> + }, \
> + .regmap_size = 1, \
> + }
> +
[Severity: Low]
Is this AIROHA_PINCTRL_GPIO macro used anywhere? It appears that only the
AIROHA_PINCTRL_GPIO_EXT variant is actually used to configure the new GPIO
functions for pins 47, 48, and 49 below, leaving this base macro unused.
> +#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val) \
> + { \
> + .name = (gpio), \
> + .regmap[0] = { \
> + AIROHA_FUNC_PWM_EXT_MUX, \
> + REG_GPIO_FLASH_MODE_CFG_EXT, \
> + (mux_val), \
> + 0 \
> + }, \
> + .regmap[1] = { \
> + AIROHA_FUNC_MUX, \
> + REG_GPIO_PON_MODE, \
> + (smux_val), \
> + (smux_val) \
> + }, \
> + .regmap_size = 2, \
> + }
> +
[ ... ]
> @@ -1431,7 +1478,7 @@ static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
> AIROHA_FUNC_MUX,
> REG_GPIO_PON_MODE,
> GPIO_PCIE_RESET2_MASK,
> - GPIO_PCIE_RESET2_MASK
> + 0
> },
> .regmap_size = 1,
> },
[Severity: High]
This is a pre-existing issue, but while this patch fixes the multiplexing
for en7581 by setting the hardware mux value to 0 here in
pcie_reset_func_group[], should the identical fix be applied to
an7583_pcie_reset_func_group[]?
Looking at an7583_pcie_reset_func_group[] further down in the file, it still
sets the hardware mux values to GPIO_PCIE_RESETx_MASK instead of 0, which
would cause the AN7583 PCIe resets to continue being incorrectly multiplexed
as GPIOs.
--
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=6
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