Re: [PATCH v3 3/3] arm64: dts: qcom: sm7125-samsung: add initial device tree

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] The QMP (SuperSpeed) USB PHY is unnecessarily enabled while the USB controller is restricted to high-speed mode without an SSPHY.
- [Low] The `rmtfs_mem` node lacks a unit address in the common dtsi but has a `reg` property appended in the board files, causing a DTC warning.
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--- Patch [3]: [PATCH v3 3/3] arm64: dts: qcom: sm7125-samsung: add initial device tree ---
commit 7ad14e43b9cfd884317a8c3a0d039dc250371474
Author: Erikas Bitovtas <[email protected]>

arm64: dts: qcom: sm7125-samsung: add initial device tree
    
Samsung Galaxy A52/A72 are devices released on atoll (SM7125) platform
in 2021. Add initial device tree for SM7125 Samsung platform with
support for:
- Framebuffer
- GPIO keys
- Hall sensor
- Vibrator
- Regulators
- Reset input
- Real-time clock
- SD card
- UFS
- USB

> diff --git a/arch/arm64/boot/dts/qcom/sm7125-samsung-a52q.dts b/arch/arm64/boot/dts/qcom/sm7125-samsung-a52q.dts
> new file mode 100644
> index 0000000000000..ecba5be8164ea
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sm7125-samsung-a52q.dts

[ ... ]

> +&rmtfs_mem {
> +	reg = <0x0 0xf4f00000 0x0 0x202000>;
> +};

[Severity: Low]
Does this trigger a unit_address_vs_reg warning in the Device Tree compiler? 

The rmtfs_mem base node is defined without a unit address in the common dtsi, 
but a reg property is appended here in the board file.

> diff --git a/arch/arm64/boot/dts/qcom/sm7125-samsung-common.dtsi b/arch/arm64/boot/dts/qcom/sm7125-samsung-common.dtsi
> new file mode 100644
> index 0000000000000..b8863e111bc4f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sm7125-samsung-common.dtsi

[ ... ]

> +&usb_1 {
> +	qcom,select-utmi-as-pipe-clk;
> +
> +	status = "okay";
> +};
> +
> +&usb_1_dwc3 {
> +	dr_mode = "peripheral";
> +	maximum-speed = "high-speed";
> +
> +	status = "okay";
> +};

[ ... ]

> +&usb_1_qmpphy {
> +	vdda-phy-supply = <&vreg_l4a_0p9>;
> +	vdda-pll-supply = <&vreg_l3c_1p2>;
> +
> +	status = "okay";
> +};

[Severity: Medium]
Is it necessary to enable the SuperSpeed QMP PHY here?

The USB controller is restricted to high-speed mode and configured to ignore 
the pipe clock from the SuperSpeed PHY via qcom,select-utmi-as-pipe-clk.

Leaving the QMP PHY enabled might unnecessarily waste power and regulator 
resources.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=3