Re: [PATCH v2 2/3] arm64: dts: qcom: ipq5424-rdp466: Enable quad SPI mode for SPI-NAND

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Enabling quad SPI transfers breaks SPI-NAND page writes because the underlying qcom_snand controller driver does not support quad write opcodes.
--

--- Patch [2]: [PATCH v2 2/3] arm64: dts: qcom: ipq5424-rdp466: Enable quad SPI mode for SPI-NAND ---
commit 1fa4c052f14795bba0cdda5777b6df317a26eaf8
Author: Md Sadre Alam <[email protected]>

arm64: dts: qcom: ipq5424-rdp466: Enable quad SPI mode for SPI-NAND

Enable quad SPI transfers for the SPI-NAND device by setting both spi-rx-
bus-width and spi-tx-bus-width to 4.

> diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
> --- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
> +++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts
> @@ -257,6 +257,8 @@ flash@0 {
>  		nand-ecc-engine = <&qpic_nand>;
>  		nand-ecc-strength = <4>;
>  		nand-ecc-step-size = <512>;
> +		spi-rx-bus-width = <4>;
> +		spi-tx-bus-width = <4>;

[Severity: High]
Will enabling a 4-bit tx bus width break page writes to this flash?

When the SPI-NAND core negotiates a 4-bit write variant (such as Quad
Program Load, opcode 0x32), the operation appears to be rejected by the
controller driver during the actual write:

drivers/spi/spi-qpic-snand.c:qcom_spi_cmd_mapping() {
	...
	case SPINAND_PROGRAM_LOAD:
		*cmd = SPINAND_PROGRAM_LOAD;
		break;
	default:
		dev_err(snandc->dev, "Opcode not supported: %u\n", opcode);
		return -EOPNOTSUPP;
}

Since qcom_spi_cmd_mapping() only maps the single-bit SPINAND_PROGRAM_LOAD
(0x84) opcode, won't the 4-bit opcodes hit the default case and return
-EOPNOTSUPP, causing all writes to fail?

>  	};
>  };

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=2