Re: [PATCH] riscv: dts: spacemit: k3: fix IMSIC guest parameters

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Reducing `riscv,guest-index-bits` to `<3>` incorrectly caps guest interrupt files and catastrophically breaks the physical MMIO layout for secondary CPUs.
--

--- Patch [1]: [PATCH] riscv: dts: spacemit: k3: fix IMSIC guest parameters ---
commit bd339af20fe829df6f685236a32dbabad41e337c
Author: GUO Ren (XuanTie) <[email protected]>

riscv: dts: spacemit: k3: fix IMSIC guest parameters

This commit updates the K3 device tree IMSIC guest configurations based on
the SpacemiT K3 User Manual. It lowers guest-index-bits and num-guest-ids
for simsic, and removes them entirely for mimsic.

Fixes: 56f37e391a62 ("riscv: dts: spacemit: add initial support for K3 SoC")

> diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
> index c3f2dce0969c0..6dce1e3aa2c91 100644
> --- a/arch/riscv/boot/dts/spacemit/k3.dtsi
> +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi

[ ... ]

> @@ -1246,9 +1246,9 @@ simsic: interrupt-controller@e0400000 {
>  					      <&cpu4_intc 9>, <&cpu5_intc 9>,
>  					      <&cpu6_intc 9>, <&cpu7_intc 9>;
>  			msi-controller;
> -			riscv,guest-index-bits = <6>;
> +			riscv,guest-index-bits = <3>;

[Severity: High]
Will reducing riscv,guest-index-bits to 3 break the physical MMIO layout
for secondary CPUs and incorrectly cap the guest interrupt files?

The IMSIC irqchip driver uses riscv,guest-index-bits to determine the
physical MMIO stride between HARTs (stride = BIT(guest-index-bits) * 4096).
By reducing this from 6 to 3, the calculated stride drops from 256 KB to
32 KB.

With a 32 KB stride, CPU 1's supervisor IMSIC file is incorrectly calculated
to be at base + 32 KB. This offset actually hits CPU 0's 8th guest interrupt
file instead of CPU 1's true supervisor file (at 256 KB).

Additionally, the AIA spec states guest files are indexed 1 to GEILEN. With
GEILEN=8, representing index 8 requires at least 4 bits. Setting
guest-index-bits = 3 mathematically limits the maximum addressable index to
7 (BIT(3) - 1), truncating the 8th guest file.

The commit message mentions that KVM will dynamically correct this via
hgeie, but KVM reads nr_guest_files directly from the irqchip driver, which
enforces the BIT(guest-index-bits) - 1 limit. Is it possible this change
will cause MSIs and IPIs for secondary CPUs to fail?

>  			riscv,hart-index-bits = <4>;
> -			riscv,num-guest-ids = <511>;
> +			riscv,num-guest-ids = <63>;
>  			riscv,num-ids = <511>;
>  		};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=1