Re: [PATCH 1/2] dt-bindings: interrupt-controller: Add Xilinx Versal NET SMMU CSR binding

On Mon, Aug 17, 2026 at 04:22:33PM +0530, Tushar Nimkar wrote:
> From: Anirudha Sarangi <[email protected]>
> 
> Add a device tree binding schema for the Xilinx Versal NET SMMU CSR
> (Control and Status Register) interrupt controller.
> 
> The SMMU CSR block acts as a vendor-specific interrupt controller
> in front of the ARM SMMUv3, providing registers to enable and clear
> standard SMMU interrupts such as EVENTQ, CMDQ_SYNC, GERROR and PRIQ.
> Interrupts must be acknowledged in this block before being forwarded
> to the parent interrupt controller (e.g. GIC).
> 
> Signed-off-by: Anirudha Sarangi <[email protected]>
> Co-developed-by: Tushar Nimkar <[email protected]>
> Signed-off-by: Tushar Nimkar <[email protected]>
> ---

b4 got only this one patch, where is the rest?

Can finally people in AMD start using b4 to send patches? How many times
I need to ask for that?


>  .../xlnx,versal-net-smmu-csr.yaml             | 85 +++++++++++++++++++
>  1 file changed, 85 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/xlnx,versal-net-smmu-csr.yaml
> 
> +required:
> +  - compatible
> +  - reg
> +  - interrupt-controller
> +  - "#interrupt-cells"
> +  - interrupts
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +
> +    iommu@ec000000 {
> +        compatible = "arm,smmu-v3";
> +        reg = <0xec000000 0x40000>;
> +        #iommu-cells = <1>;
> +        dma-coherent;
> +        interrupt-names = "eventq", "gerror", "priq";
> +        interrupt-parent = <&smmu_irq_csr>;
> +        interrupts = <0>, <2>, <3>;
> +    };

Drop node irrelevant.

> +
> +    smmu_irq_csr: interrupt-controller@eca10000 {

Drop unused label

> +        compatible = "xlnx,versal-net-smmu-csr";
> +        reg = <0xeca10000 0x1000>;
> +        interrupt-controller;
> +        #interrupt-cells = <1>;
> +        interrupt-parent = <&gic>;
> +        interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
> +    };
> -- 
> 2.34.1
> 
>