Re: [PATCH 1/2] dt-bindings: interrupt-controller: Add Xilinx Versal NET SMMU CSR binding
Tushar Nimkar <[email protected]>
| Newsgroups | org.kernel.vger.linux-devicetree |
|---|---|
| Message-ID | <[email protected]> |
On 8/18/2026 12:48 PM, Michal Simek wrote: > > > On 8/18/26 09:03, Krzysztof Kozlowski wrote: >> On Mon, Aug 17, 2026 at 04:22:33PM +0530, Tushar Nimkar wrote: >>> From: Anirudha Sarangi <[email protected]> >>> >>> Add a device tree binding schema for the Xilinx Versal NET SMMU CSR >>> (Control and Status Register) interrupt controller. >>> >>> The SMMU CSR block acts as a vendor-specific interrupt controller >>> in front of the ARM SMMUv3, providing registers to enable and clear >>> standard SMMU interrupts such as EVENTQ, CMDQ_SYNC, GERROR and PRIQ. >>> Interrupts must be acknowledged in this block before being forwarded >>> to the parent interrupt controller (e.g. GIC). >>> >>> Signed-off-by: Anirudha Sarangi <[email protected]> >>> Co-developed-by: Tushar Nimkar <[email protected]> >>> Signed-off-by: Tushar Nimkar <[email protected]> >>> --- >> >> b4 got only this one patch, where is the rest? >> >> Can finally people in AMD start using b4 to send patches? How many times >> I need to ask for that? > > Not sure what you want me to say about it. I don't think that this is > related to AMD but only individual developers. > > There are also other tools for doing it not just b4. Everybody got > these instructions but it is up to everybody to follow them. When > something is sent out I can't do anything with it. (And internally > this was sent as threaded multiple times). > My bad !! Something went bad while sending outside. Krzysztof, The other patch link - https://lore.kernel.org/all/[email protected]/ and I will fix this. I apologize. > Thanks, > Michal >