[PATCH v3 1/4] dt-bindings: edac: Add bindings for Xilinx Versal XilSEM

Update versal edac device tree bindings for
Versal Soft Error Mitigation (XilSEM).

Signed-off-by: Rama devi Veggalam <[email protected]>
---
Changes in v3:
- Merged XilSEM edac with Versal Edac

Changes in v2:
- Changed "xlnx,versal-xilsem-edac" to constant
- Removed "compatible: in required section
- Removed "|" in description
- Removed "items" in compatible
- Fixed indentation in examples
- Updated title and description
---
 .../xlnx,versal-ddrmc-edac.yaml               | 22 ++++++++++++++++---
 1 file changed, 19 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml b/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml
index 12f8e9f350bc..568d2af7de81 100644
--- a/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml
@@ -4,17 +4,31 @@
 $id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-ddrmc-edac.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Xilinx Versal DDRMC (Integrated DDR Memory Controller)
+title: Xilinx Versal DDRMC (Integrated DDR Memory Controller) and Soft Error Mitigation (XilSEM)
 
 maintainers:
   - Shubhrajyoti Datta <[email protected]>
   - Sai Krishna Potthuri <[email protected]>
+  - Rama Devi Veggalam <[email protected]>
 
 description:
   The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/
   4X memory interfaces. Versal DDR memory controller has an optional ECC support
   which correct single bit ECC errors and detect double bit ECC errors.
 
+  Xilinx Versal Soft Error Mitigation (XilSEM) is part of the
+  Platform Loader and Manager (PLM) which runs on the
+  Platform Management Controller (PMC). XilSEM is responsible for reporting
+  and optionally correcting soft errors in Configuration Memory of Versal.
+  The Configuration Memory includes Configuration RAM and
+  Network on Chip (NoC) peripheral interconnect (NPI) Registers.
+
+  The memory is scanned by a hardware controller in the Versal Programmable
+  Logic (PL). During the scan, if the controller detects any error, be it
+  correctable or uncorrectable, it reports the error to PLM.
+  The XilSEM on PLM performs the error validation and notifies the errors to user application.
+
+
 properties:
   compatible:
     const: xlnx,versal-ddrmc
@@ -23,11 +37,13 @@ properties:
     items:
       - description: DDR Memory Controller registers
       - description: NOC registers corresponding to DDR Memory Controller
+      - description: SEM RTCA Controller registers
 
   reg-names:
     items:
       - const: base
       - const: noc
+      - const: semrtca
 
   interrupts:
     maxItems: 1
@@ -49,8 +65,8 @@ examples:
       #size-cells = <2>;
       memory-controller@f6150000 {
         compatible = "xlnx,versal-ddrmc";
-        reg = <0x0 0xf6150000 0x0 0x2000>, <0x0 0xf6070000 0x0 0x20000>;
-        reg-names = "base", "noc";
+        reg = <0x0 0xf6150000 0x0 0x2000>, <0x0 0xf6070000 0x0 0x20000>, < 0x00 0xf2014050 0x00 0xc4>;
+        reg-names = "base", "noc" , "semrtca";
         interrupt-parent = <&gic>;
         interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
       };
-- 
2.23.0