Re: [PATCH 0/4] EDAC/altera: Add support for Agilex5 platform

Hi Dinh,

Krzysztof pointed out that my earlier standalone patches were confusing.
They were based on top of this series and were unparseable by tooling,
so I am sending the changes here instead for you to fold into the v2.

Feel free to take them with
Signed-off-by: Rounak Das <[email protected]>

Two other things from applying the series:

- Patch 2/4 has "unsigned long flag = {unsigned long)device->edac->flag;"
  with a brace instead of a paren, so it does not build on its own.
  Patch 3/4 fixes it in passing, which breaks bisect.

- I have not done the per-variant interrupts/interrupt-names constraints
  Krzysztof asked for in 1/4.

Thanks,
Rounak

1) Patch 1/4: merge the s10/agilex5 compatibles into one enum, since
   they share the a10 fallback.

diff --git a/Documentation/devicetree/bindings/edac/altr,socfpga-ecc-manager.yaml b/Documentation/devicetree/bindings/edac/altr,socfpga-ecc-manager.yaml
index 2ccb0f216318..34af88988b84 100644
--- a/Documentation/devicetree/bindings/edac/altr,socfpga-ecc-manager.yaml
+++ b/Documentation/devicetree/bindings/edac/altr,socfpga-ecc-manager.yaml
@@ -20,10 +20,9 @@ properties:
   compatible:
     oneOf:
       - items:
-          - const: altr,socfpga-s10-ecc-manager
-          - const: altr,socfpga-a10-ecc-manager
-      - items:
-          - const: altr,socfpga-agilex5-ecc-manager
+          - enum:
+              - altr,socfpga-s10-ecc-manager
+              - altr,socfpga-agilex5-ecc-manager
           - const: altr,socfpga-a10-ecc-manager
       - const: altr,socfpga-a10-ecc-manager
       - const: altr,socfpga-ecc-manager

2) Patch 2/4: use an enum instead of defines. SOCFPGA_A10 is 0 so the
   Arria10 match entry, which has no match data, maps to it naturally.
   The values for S10 and AGILEX5 are unchanged.

diff --git a/drivers/edac/altera_edac.h b/drivers/edac/altera_edac.h
index 30e35da7eb6a..79b51f051183 100644
--- a/drivers/edac/altera_edac.h
+++ b/drivers/edac/altera_edac.h
@@ -372,8 +372,11 @@ enum altr_agilex5_irq_idx {
 #define ECC_READ_EOVR                     0x2
 #define ECC_READ_EDOVR                    0x3
 
-#define SOCFPGA_S10                       0x1
-#define SOCFPGA_AGILEX5                   0x2
+enum altr_socfpga_platform {
+	SOCFPGA_A10,
+	SOCFPGA_S10,
+	SOCFPGA_AGILEX5,
+};
 
 struct altr_edac_device_dev;
 
-- 
2.50.1 (Apple Git-155)