Re: [PATCH v2 1/2] x86/mce/amd: Fix inverted interrupt enablement during storm handling

On Mon, Aug 17, 2026 at 12:51:08PM -0600, Jasjeet Rangi wrote:
> Inverting `on` in mce_amd_handle_storm() alone is not enough because
> clear_bank() will immediately and unconditionally enable the interrupt
> again.

And?

What would happen then?

Did you read my previous reply?

"The thresholding interrupt should not be a problem because with increased
polling frequency during a storm, we should not be really getting thresholding
interrupts because the polling code will pick up all MCEs that get logged,
first."

Or do you have somehing in mind here which I cannot guess?

> Also, the threshold is sysfs configurable. For example, if the
> threshold is set to 1, even when storm handling is on there will be
> effectively no polling.

Yeah, we don't protect users from themselves, you know :)

> On Intel the threshold is temporarily set to a very high value because
> the goal is to effectively disable interrupts for CEs without disabling
> interrupts for certain UEs signaled via CMCI. In older kernels the Intel
> driver used to disable the interrupt.

We do clear MCi_MISC[ErrCnt] to 0 so that's the "highest' value we can do
before we raise an interrupt there :)

Thx.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette