Re: [PATCH v2 1/2] x86/mce/amd: Fix inverted interrupt enablement during storm handling

On Wed, Aug 19, 2026 at 7:07 AM Yazen Ghannam <[email protected]> wrote:
>
> IMO, disabling the interrupt is the best way to manage the storm. The
> reason for Intel to set a high limit is to keep the interrupt enabled.
> The reason to keep the interrupt enabled is because the same interrupt
> line is used for reporting "uncorrectable,no action" errors. This isn't
> necessary on AMD because there's a separate interrupt line for those
> errors: Deferred error interrupt.

Agreed. Also that was the original intent of the patch that this
thread/patch is fixing. From the commit message for 5c4663ed1eac
("x86/mce: Handle AMD threshold interrupt storms"):
```
But, unlike CMCI, do not set thresholds and reduce interrupt rate on
a storm. Rather, disable the interrupt on the corresponding CPU and bank.
Re-enable back the interrupts if enough consecutive polls of the bank show no
corrected errors (30, as programmed by Intel).
```

> It's fair to set a low threshold limit. Some users want to see corrected
> errors without needing to poll. And they'd like to see them ASAP.
>
> The threshold limit isn't much of a contributor to interrupt storms. A
> stuck bit/failing device will likely trigger a storm whether the limit
> is '1' or '4095'.
Agreed. Thanks for clarifying.

Thanks,
Jasjeet