Re: [PATCH v4 04/21] pinctrl: starfive: Add StarFive JHB100 sys0 controller driver

On Sa, 2026-08-01 at 00:26 -0700, Changhuang Liang wrote:
> Add pinctrl driver for StarFive JHB100 SoC System-0(sys0) pinctrl
> controller.
>=20
> Simultaneously add a generic pinctrl driver framework for registering
> the pinctrl of other domains (sys1, sys2, and so on) in the JHB100 SoC.
>=20
> Co-developed-by: Lianfeng Ouyang <[email protected]>
> Signed-off-by: Lianfeng Ouyang <[email protected]>
> Signed-off-by: Alex Soo <[email protected]>
> Signed-off-by: Changhuang Liang <[email protected]>
> ---
>  MAINTAINERS                                   |    9 +
>  drivers/pinctrl/starfive/Kconfig              |   20 +
>  drivers/pinctrl/starfive/Makefile             |    3 +
>  .../starfive/pinctrl-starfive-jhb100-sys0.c   |  119 ++
>  .../starfive/pinctrl-starfive-jhb100.c        | 1456 +++++++++++++++++
>  .../starfive/pinctrl-starfive-jhb100.h        |  159 ++
>  6 files changed, 1766 insertions(+)
>  create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys0=
.c
>  create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100.c
>  create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100.h
>=20
[...]
> diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys0.c b/dr=
ivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys0.c
> new file mode 100644
> index 000000000000..ed23c0c43960
> --- /dev/null
> +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-sys0.c
> @@ -0,0 +1,119 @@
[...]
> +int jhb100_pinctrl_probe(struct platform_device *pdev)
> +{
> +	struct device *dev =3D &pdev->dev;
> +	struct gpio_irq_chip *girq;
> +	const struct jhb100_pinctrl_domain_info *info;
> +	struct jhb100_pinctrl *sfp;
> +	struct pinctrl_desc *jhb100_pinctrl_desc;
> +	const struct starfive_pinctrl_regs *pinctrl_regs;
> +	struct reset_control *rst;
> +	struct clk *clk;
> +	int ret;
> +
> +	info =3D of_device_get_match_data(&pdev->dev);
> +	if (!info)
> +		return -ENODEV;
> +
> +	pinctrl_regs =3D info->regs;
> +
> +	sfp =3D devm_kzalloc(dev, sizeof(*sfp), GFP_KERNEL);
> +	if (!sfp)
> +		return -ENOMEM;
> +
> +	sfp->base =3D devm_platform_ioremap_resource(pdev, 0);
> +	if (IS_ERR(sfp->base))
> +		return PTR_ERR(sfp->base);
> +
> +	clk =3D devm_clk_get_optional_enabled(dev, NULL);
> +	if (IS_ERR(clk))
> +		return dev_err_probe(dev, PTR_ERR(clk), "could not get & enable clock\=
n");
> +
> +	rst =3D devm_reset_control_array_get_optional_shared(dev);

The dt-binding specifies a single reset control. Why does this use the
array API?

Using devm_reset_control_get_optional_shared_deasserted() could
simplify this a little bit.

regards
Philipp