Re: [PATCH] pinctrl: qcom: nord: Split QUP1 SE2/SE3 into lane-pair functions
Konrad Dybcio <[email protected]>
| Newsgroups | org.kernel.vger.linux-gpio,org.kernel.vger.linux-arm-msm,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel,org.kernel.vger.stable |
|---|---|
| Message-ID | <[email protected]> |
On 8/19/26 5:23 PM, Shawn Guo wrote: > QUP1 SE2 and SE3 pack all four of their lanes pair-wise onto only two > pins each: lanes 0/1 (I2C SDA/SCL) at mux value 2 and lanes 2/3 (UART > TX/RX) at mux value 1, on gpio127/gpio128 and gpio129/gpio130 > respectively. [...] > + msm_mux_qup1_se2_01, other drivers where this is necessary stick an 'l' before the lane indices, e.g. se2_l2, let's keep this The bindings change must be separate Konrad