Re: [PATCH] pinctrl: qcom: nord: Split QUP1 SE2/SE3 into lane-pair functions

On Mon, Aug 24, 2026 at 10:44 AM Konrad Dybcio
<[email protected]> wrote:
>
> On 8/20/26 3:15 AM, Shawn Guo wrote:
> > On Wed, Aug 19, 2026 at 05:27:34PM +0200, Konrad Dybcio wrote:
> >> On 8/19/26 5:23 PM, Shawn Guo wrote:
> >>> QUP1 SE2 and SE3 pack all four of their lanes pair-wise onto only two
> >>> pins each: lanes 0/1 (I2C SDA/SCL) at mux value 2 and lanes 2/3 (UART
> >>> TX/RX) at mux value 1, on gpio127/gpio128 and gpio129/gpio130
> >>> respectively.
> >>
> >> [...]
> >>
> >>> +   msm_mux_qup1_se2_01,
> >>
> >> other drivers where this is necessary stick an 'l' before the
> >> lane indices, e.g. se2_l2, let's keep this
> >
> > I can see that for single lane function. But for lane-pair function,
> > it's not a new thing with nord, and the naming convention seems to be
> > without 'l', based on what I see from shikra, eliza, hawi and maili
> > drivers.
>
> Hm, seems like that happened by oversight, but yeah let's stick to it
> now.
>
> >> The bindings change must be separate
> >
> > I understand that's mandatory for new feature changes, but for such
> > a bug fix where both binding and driver changes are closely coupled,
> > it seems more reasonable to not split.
>
> Up to brgl
>

I'm fine with this. Krzyszof, Rob, Conor: any objections?

Thanks,
Bartosz