Re: [PATCH v8 04/11] arm64: errata: Require Apple IMPDEF PMUv3 traps on all CPUs

Akihiko Odaki <[email protected]> Sat, 1 Aug 2026 15:34:11 +0900
Newsgroups org.kernel.vger.linux-hardening,dev.linux.lists.kvmarm,org.infradead.lists.linux-arm-kernel,org.kernel.vger.kvm,org.kernel.vger.linux-doc,org.kernel.vger.linux-kernel,org.kernel.vger.linux-kselftest
Message-ID <[email protected]>
On 2026/08/01 1:50, Will Deacon wrote:
> On Fri, Jul 10, 2026 at 08:14:58PM +0900, Akihiko Odaki wrote:
>> KVM relies on ARM64_WORKAROUND_PMUV3_IMPDEF_TRAPS as a system-wide
>> precondition for PMUv3 emulation on affected Apple CPUs. A local CPU
>> erratum is too weak for that: once the workaround is enabled, a late CPU
>> that misses it may still be onlined.
>>
>> Make the workaround an all-early-CPU capability instead. The matcher is
>> still local because it depends on MIDR_EL1, but the capability is only
>> advertised if all early CPUs match, and late CPUs that miss it are
>> rejected once the capability is enabled.
>>
>> Assisted-by: Codex:gpt-5.5
>> Signed-off-by: Akihiko Odaki <[email protected]>
>> ---
>>   arch/arm64/kernel/cpu_errata.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
>> index 476a37c82108..14ce49d693c4 100644
>> --- a/arch/arm64/kernel/cpu_errata.c
>> +++ b/arch/arm64/kernel/cpu_errata.c
>> @@ -964,7 +964,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
>>   	{
>>   		.desc = "Apple IMPDEF PMUv3 Traps",
>>   		.capability = ARM64_WORKAROUND_PMUV3_IMPDEF_TRAPS,
>> -		.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
>> +		.type = ARM64_CPUCAP_EARLY_LOCAL_CPU_FEATURE,
> 
> I always get tangled in knots with this code, but does this correctly
> handle the case where the boot/early CPUs don't have the impdef PMU
> feature but late-onlined CPUs do? I'm not sure we configure the traps
> correctly in that case but this is all gloriously undocumented.
It's not only you but Fuad and Sashiko also had the same question:
https://lore.kernel.org/qemu-devel/[email protected]/

The answer is that we simply don't enable hypervisor traps. Accessing 
PMUv3 registers will be UNDEFINED on all CPUs, enforcing the 
architectural behavior system-wide.

I plan to change the patch message to clarify this in the next version.

Regards,
Akihiko Odaki