Re: [PATCH v2 1/2] dt-bindings: i2c: Add Qualcomm I2C target controller

On Sun, Aug 02, 2026 at 06:43:30PM +0530, Viken Dadhaniya wrote:
> QDU1000 and related Qualcomm SoCs include a dedicated I2C target
> controller that operates exclusively in target mode. It is a distinct
> IP from the Qualcomm I2C master controllers (GENI, QUP) with a
> different register interface, so it requires its own binding.
> 
> Document the MMIO region, interrupt, XO and AHB clocks, interconnect
> path, and optional pinctrl states for the controller.
> 
> Signed-off-by: Viken Dadhaniya <[email protected]>
> ---
>  .../devicetree/bindings/i2c/qcom,i2c-target.yaml   | 84 ++++++++++++++++++++++

Filename must match compatible.

>  1 file changed, 84 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-target.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-target.yaml
> new file mode 100644
> index 000000000000..1e34e874cc4c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-target.yaml
> @@ -0,0 +1,84 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/i2c/qcom,i2c-target.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm I2C Target Controller
> +
> +maintainers:
> +  - Mukesh Kumar Savaliya <[email protected]>
> +  - Viken Dadhaniya <[email protected]>
> +
> +description:
> +  Dedicated hardware IP found on Qualcomm SoCs that operates exclusively
> +  as an I2C target (slave) device on the bus. Supports FIFO (PIO) mode
> +  for data transfer.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - qcom,qdu1000-i2c-target
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: XO reference clock
> +      - description: AHB bus clock
> +
> +  clock-names:
> +    items:
> +      - const: xo
> +      - const: ahb
> +
> +  interconnects:
> +    maxItems: 1
> +
> +  interconnect-names:
> +    const: i2c

Pretty useless name, drop the interconnect-names.

> +
> +  pinctrl-0: true
> +  pinctrl-1: true
> +
> +  pinctrl-names:
> +    items:
> +      - const: default
> +      - const: sleep
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - clocks
> +  - clock-names
> +  - interconnects
> +  - interconnect-names
> +
> +allOf:
> +  - $ref: /schemas/i2c/i2c-controller.yaml#

This wasn't here before. Is this a controller or a target? Now I am
confused.

> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/clock/qcom,qdu1000-gcc.h>
> +    #include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h>
> +
> +    i2c@88ca000 {
> +        compatible = "qcom,qdu1000-i2c-target";
> +        reg = <0x88ca000 0x64>;
> +        clocks = <&gcc GCC_SM_BUS_XO_CLK>, <&gcc GCC_SM_BUS_AHB_CLK>;
> +        clock-names = "xo", "ahb";
> +        interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
> +        #address-cells = <1>;
> +        #size-cells = <0>;

How is this valid?

What sort of children the target has? What does it do with these
children?

> +        interconnect-names = "i2c";
> +        interconnects = <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SMBUS_CFG 0>;
> +    };
> +...
> 
> -- 
> 2.34.1
>