Re: [PATCH 3/3] iio: adc: ti-ads112c14: add support for buffered read
David Lechner <[email protected]>
| Newsgroups | org.kernel.vger.linux-iio,org.kernel.vger.linux-kernel |
|---|---|
| Message-ID | <[email protected]> |
On 7/23/26 6:25 PM, Jonathan Cameron wrote: > On Tue, 21 Jul 2026 18:23:58 -0500 > David Lechner <[email protected]> wrote: > >> On 7/19/26 7:55 PM, Jonathan Cameron wrote: >>> On Tue, 14 Jul 2026 19:19:32 -0500 >>> "David Lechner (TI)" <[email protected]> wrote: >>> >>>> Add support for buffered reads using a triggered buffer. >>>> >>>> The device has a continuous conversion mode, but that can only be used >>>> with one channel at a time since there is nothing like a sequencer to >>>> support that in hardware. Instead, we use single-shot reads like we do >>>> for direct reads to be able to read multiple channels. >>>> >>>> Support for continuous conversion mode could be added in the future if >>>> needed via a 2nd buffer. >>> >>> How about enabling that if only one channel is requested? I vaguely recall >>> us doing that for another driver (though I might be dreaming :) I did >>> see your comment in the cover letter about it affecting timing and that >>> making life complex. Fine to leave considering this for another day >>> but maybe don't suggest a particular solution here. >>> >> Actually, my latest thought it to do it by trigger type. This chip has >> a DRDY interrupt that can be used as the trigger for the continuous >> conversion mode but we need some software trigger to the single-shot >> mode. It think this would take care of the timing issues as well. >> >> The logic would be that if the self trigger (DRDY) is selected in >> the trigger/current_trigger attribute, then buffered read will use >> continuous mode and fail if more than one channel is enabled. If >> another (software) trigger is enabled, then use single-shot mode >> and allow multiple channels. > > Hmm. Bit unintuitive but can't really be helped. > >> >> The timing issue is that (or will be since I haven't sent the relevant >> patches yet) there is a settling delay before the first sample. For >> single-shot mode, every sample is considered the first sample (because >> it is "single"), so the chip applies this settling time on every sample. >> So it might be good enough to just document that as a quirk of software >> triggers for this particular chip since they would be using single-shot >> mode? >> > This is where it gets messy if settling time is reported. I guess acceptable > given it doesn't make that much sense for an external trigger anyway. > In theory if the settling time has to happen each single shot, we could > just merge it into sampling frequency (as no longer depends on whether > channel changes or not) but then we have to make that dependent on whether > it is the devices own trigger or not. Messy. I guess one to paper over > as a quirk / corner case and document as you say. Yes, this is the direction I am leaning as well. The input chopping feature that we have been talking about has a similar issue. In addition to doubling the sample period, it also includes the settling time (2x as well) minus a few clock cycles. Even messier.