Re: [PATCH 4/5] spi: ma35d1-qspi: Add DTR support
Mark Brown <[email protected]>
| Newsgroups | org.kernel.vger.linux-kernel,org.infradead.lists.linux-arm-kernel,org.kernel.vger.linux-spi |
|---|---|
| Message-ID | <[email protected]> |
On Thu, Aug 13, 2026 at 10:00:24AM +0200, Miquel Raynal wrote: > The controller has DTR support, a bit must be set for it. The behaviour > is interesting though, as the speed won't improve when enabled. This is > because there seems to be an internal divisor (/2) which keeps the rate > equal when DTR is enabled. As a result, this commit also doubles the > target bus speed, which in practice does not happen. This way, there is > a real gain: > @@ -567,7 +577,8 @@ static int nuvoton_qspi_transfer_one(struct spi_controller *ctlr, > buswidth = 2; > } > > - ret = nuvoton_qspi_configure_bus(spi, buswidth, dir, xfer->speed_hz); > + ret = nuvoton_qspi_configure_bus(spi, buswidth, dir, xfer->speed_hz, > + xfer->dtr_mode); > if (ret) > return ret; This needs ctlr->dtr_caps configuring, otherwise the validation will block it - only the _mem_caps were updated.
signature.asc
(application/pgp-signature, 488 B)
-----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEreZoqmdXGLWf4p/qJNaLcl1Uh9AFAmp+OEIACgkQJNaLcl1U h9DZ2Af+Nhsdzbp64ywAW88mtOuZ/FvF8klN/5pJZjRQzBM9u/Xw6tkIa1wfMTEa rubL4TJK2bNU7LG3vghKhkFZ9Z9E1GPYNHOPzQ42E0BWI/T+sCeMQdQKcCHWpiFq tADVc3oMY8vjymgRSzDU53flhddz6GREVOgoPy+LrRrjktCu84481I8YbMVjZqqh BXc4yo15EgqxKK/qckLVqpq1bNS133PJrA1xPT5gQSsPfr19uHRs22AGot0Vdd2y mSchqod0ciOlSQBQ+k9YfiYwpacrPZ9qIm9HJgULjKyk8vu2YZ9m8sK7BVAPSeAE cH4Wwpf6YPp6rElv0Wzo4CDGbtmTEA== =mY/B -----END PGP SIGNATURE-----