[PATCH 1/3] m68k: coldfire/5441x: define RSR cause bits

The Reset Controller Module on the m5441x already had its RCR and RSR
register addresses declared in this header, but the layout of RSR was
missing. Add the bit definitions for every cause documented in the
MCF54418 Reference Manual, chapter 12.3.2:

  bit 7  Reserved
  bit 6  Reserved
  bit 5  SOFT       software reset                          0x20
  bit 4  LOC        PLL loss of clock                       0x10
  bit 3  POR        power-on reset                          0x08
  bit 2  EXT        external reset pin                      0x04
  bit 1  WDRCORE    core watchdog timer timeout             0x02
  bit 0  LOL        PLL loss of lock                        0x01

The RSR register at 0xec090001 is 8-bit read-only and latches the
cause (or causes) of the most recent reset until the next one.

Signed-off-by: Jean-Michel Hautbois <[email protected]>
---
 arch/m68k/include/asm/m5441xsim.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/m68k/include/asm/m5441xsim.h b/arch/m68k/include/asm/m5441xsim.h
index f48cf63bd782..3c086274f4da 100644
--- a/arch/m68k/include/asm/m5441xsim.h
+++ b/arch/m68k/include/asm/m5441xsim.h
@@ -28,6 +28,13 @@
 #define	MCF_RCR_SWRESET		0x80		/* Software reset bit */
 #define	MCF_RCR_FRCSTOUT	0x40		/* Force external reset */
 
+#define	MCF_RSR_SOFT		0x20		/* Last reset caused by software */
+#define	MCF_RSR_LOC		0x10		/* Last reset caused by PLL loss of clock */
+#define	MCF_RSR_POR		0x08		/* Last reset caused by power-on */
+#define	MCF_RSR_EXT		0x04		/* Last reset caused by external pin */
+#define	MCF_RSR_WDRCORE		0x02		/* Last reset caused by core watchdog */
+#define	MCF_RSR_LOL		0x01		/* Last reset caused by PLL loss of lock */
+
 /*
  *  Interrupt Controller Modules.
  */

-- 
2.39.5