Re: [PATCH RESEND v9 6/9] media: qcom: camss: csiphy-3ph: Add Gen2 v1.1 MIPI CSI-2 C-PHY init

David Heidelberg <[email protected]>
Newsgroups org.kernel.vger.linux-media,org.kernel.vger.linux-arm-msm,org.kernel.vger.linux-kernel,org.kernel.vger.phone-devel
Message-ID <[email protected]> 
On 29/07/2026 23:35, Frank Li wrote:
> On Wed, Jul 29, 2026 at 10:20:01PM +0200, David Heidelberg wrote:
>> Add a PHY configuration sequence for the sdm845 which uses a Qualcomm
>> Gen 2 version 1.1 CSI-2 PHY.
>>
>> The PHY can be configured as two phase or three phase in C-PHY or D-PHY
>> mode.
> 
> too much or, according to my understand D-PHY use 2 phase,  C-PHY use 3
> phase?
> 
> The PHY can be configured as two phase (D-PHY) or three phase (C-PHY) ?

Yes, I'll address the wrong wording in the next version then :)

> 
> Frank
> 
>> This configuration supports three-phase C-PHY mode.
>>
>> Acked-by: Cory Keitz <[email protected]>
>> Signed-off-by: David Heidelberg <[email protected]>
>> ---
>>   .../platform/qcom/camss/camss-csiphy-3ph-1-0.c     | 78 +++++++++++++++++++++-
>>   1 file changed, 76 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
>> index 5c07aa9d19c51..83de89a88dbb1 100644
>> --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
>> +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
>> @@ -45,16 +45,23 @@
>>
>>   #define CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(offset, n)	((offset) + 0x4 * (n))
>>   #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE	BIT(7)
>>   #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B	BIT(0)
>>   #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID	BIT(1)
>>   #define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(offset, common_status_offset, n) \
>>   	((offset) + (common_status_offset) + 0x4 * (n))
>>
>> +#define CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(n) \
>> +	(0x0100 + ((n) * 0x4))
>> +#define CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(n) \
>> +	(0x0300 + ((n) * 0x4))
>> +#define CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(n) \
>> +	(0x0500 + ((n) * 0x4))
>> +
>>   #define CSIPHY_DEFAULT_PARAMS		0
>>   #define CSIPHY_LANE_ENABLE		1
>>   #define CSIPHY_SETTLE_CNT_LOWER_BYTE	2
>>   #define CSIPHY_SETTLE_CNT_HIGHER_BYTE	3
>>   #define CSIPHY_DNP_PARAMS		4
>>   #define CSIPHY_2PH_REGS			5
>>   #define CSIPHY_3PH_REGS			6
>>   #define CSIPHY_SKEW_CAL			7
>> @@ -141,16 +148,17 @@ csiphy_lane_regs lane_regs_sa8775p[] = {
>>   	{0x0460, 0xFD, 0x00, CSIPHY_DEFAULT_PARAMS},
>>   	{0x0464, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
>>   	{0x065C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>>   	{0x0660, 0xFD, 0x00, CSIPHY_DEFAULT_PARAMS},
>>   	{0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
>>   };
>>
>>   /* GEN2 1.0 2PH */
>> +/* 5 entries: clock + 4 lanes */
>>   static const struct
>>   csiphy_lane_regs lane_regs_sdm845[] = {
>>   	{0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
>>   	{0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
>>   	{0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
>>   	{0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
>>   	{0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
>>   	{0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS},
>> @@ -215,16 +223,82 @@ csiphy_lane_regs lane_regs_sdm845[] = {
>>   	{0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
>>   	{0x060C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
>>   	{0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
>>   	{0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
>>   	{0x0660, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>>   	{0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
>>   };
>>
>> +/* GEN2 1.0 3PH */
>> +/* 3 entries: 3 lanes (C-PHY) */
>> +static const struct
>> +csiphy_lane_regs lane_regs_sdm845_3ph[] = {
>> +	{CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(23), 0x43, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(26), 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(27), 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(1),  0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(3),  0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
>> +	{CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(2),  0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
>> +	{CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(5),  0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(20), 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(6),  0x3e, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(7),  0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(8),  0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(9),  0x7f, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(10), 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(11), 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(17), 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(24), 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(51), 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(25), 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN1_CSI_3PH_CTRLn_ADDR(55), 0x51, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +
>> +	{CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(23), 0x43, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(26), 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(27), 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(1),  0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(3),  0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
>> +	{CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(2),  0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
>> +	{CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(5),  0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(20), 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(6),  0x3e, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(7),  0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(8),  0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(9),  0x7f, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(10), 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(11), 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(17), 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(24), 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(51), 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(25), 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN3_CSI_3PH_CTRLn_ADDR(55), 0x51, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +
>> +	{CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(23), 0x43, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(26), 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(27), 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(1),  0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(3),  0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
>> +	{CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(2),  0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
>> +	{CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(5),  0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(20), 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(6),  0x3e, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(7),  0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(8),  0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(9),  0x7f, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(10), 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(11), 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(17), 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(24), 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(51), 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(25), 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +	{CSIPHY_LN5_CSI_3PH_CTRLn_ADDR(55), 0x51, 0x00, CSIPHY_DEFAULT_PARAMS},
>> +
>> +};
>> +
>>   /* GEN2 1.1 2PH */
>>   static const struct
>>   csiphy_lane_regs lane_regs_sc8280xp[] = {
>>   	{0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
>>   	{0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
>>   	{0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
>>   	{0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
>>   	{0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
>> @@ -1169,18 +1243,18 @@ static void csiphy_lanes_enable(struct csiphy_device *csiphy,
>>   	int i;
>>
>>   	switch (csiphy->camss->res->version) {
>>   	case CAMSS_845:
>>   		if (c->phy_cfg == V4L2_MBUS_CSI2_DPHY) {
>>   			regs->lane_regs = &lane_regs_sdm845[0];
>>   			regs->lane_array_size = ARRAY_SIZE(lane_regs_sdm845);
>>   		} else if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
>> -			regs->lane_regs = NULL;
>> -			regs->lane_array_size = 0;
>> +			regs->lane_regs = &lane_regs_sdm845_3ph[0];
>> +			regs->lane_array_size = ARRAY_SIZE(lane_regs_sdm845_3ph);
>>   		}
>>   		break;
>>   	case CAMSS_2290:
>>   	case CAMSS_6150:
>>   		if (c->phy_cfg == V4L2_MBUS_CSI2_DPHY) {
>>   			regs->lane_regs = &lane_regs_qcm2290[0];
>>   			regs->lane_array_size = ARRAY_SIZE(lane_regs_qcm2290);
>>   		} else if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
>>
>> --
>> 2.53.0
>>

-- 
David Heidelberg
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