Re: [PATCH 1/4] dt-bindings: media: qcom,sc7280-venus: Add dma-coherent property

Rob Herring <[email protected]>
Newsgroups org.kernel.vger.linux-media,org.kernel.vger.linux-arm-msm,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel,org.kernel.vger.stable
Message-ID <[email protected]>
On Fri, Aug 14, 2026 at 10:58:47AM +0530, Vishnu Reddy wrote:
> 
> On 8/11/2026 7:21 PM, Rob Herring wrote:
> > On Sat, Aug 01, 2026 at 01:07:27PM +0530, Vishnu Reddy wrote:
> >> While testing with some higher resolution clips, the venus hardware
> >> triggers a fault due to wrong input data being received. Corruption
> >> was also observed in the captured output when the client dumped it
> >> to a file.
> >>
> >> On debugging, this was traced to the venus node not declaring
> >> dma-coherent. As a result, DMA buffers shared between the CPU and the
> >> venus video hardware/controller are not guaranteed to be I/O coherent:
> >> CPU writes to an input buffer can remain in CPU caches without being
> >> visible to the video hardware when it reads the same buffer, so the
> >> hardware receives input data that does not match what the CPU wrote.
> >> Likewise, on the capture path, data written by the video hardware to
> >> the output buffer may not be visible to the CPU, so the client reads
> >> stale or partial data, resulting in corruption.
> > The only side effect of 'dma-coherent' not being present should be doing 
> > unnecessary cache flushes. It should still work. Maybe you are missing 
> > some DMA API sync functions?
> 
> dma-coherent tells the kernel that this device DMA path is hardware-coherent,
> so the SMMU maps its buffers as cacheable. That attribute is what causes the
> coherent interconnect to snoop CPU cache lines on every VPU transaction, so
> hardware keeps CPU caches and VPU visible memory in sync — which is why the
> dma-coherent property lets us skip the unnecessary cache clean/invalidate.
> 
> If a device doesn't support I/O coherence, its buffers would instead be mapped
> non-cacheable, no snooping would occur, and the driver would need explicit
> dma_sync_*() calls at each transition.

The driver should have dma_sync_*() calls regardless. Even if cache 
flush/invalidate are not needed, IIRC the calls still provide barriers 
which may be needed.

Rob
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