Re: [PATCH v8 1/3] dt-bindings: mmc: sdhci-msm: add ICE phandle
Ulf Hansson <[email protected]> Mon, 6 Jul 2026 17:46:05 +0200
| Newsgroups | org.kernel.vger.linux-mmc,org.kernel.vger.linux-arm-msm,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel |
|---|---|
| Message-ID | <CAPx+jO8t_kQ5q4XmNJoJ1nR4Kro-2M1s_Xj93qxuFUW7VPQpTw@mail.gmail.com> |
On Mon, Jun 29, 2026 at 9:36 AM Kuldeep Singh <[email protected]> wrote: > > From: Neeraj Soni <[email protected]> > > On newer Qualcomm SoCs (starting with sc7280/kodiak), ICE is modelled > as a dedicated DT node. Add the optional qcom,ice phandle to reference > that node from the SDHCI controller. > > When qcom,ice is present, disallow an embedded ICE register region in > the SDHCI node to avoid double modelling. Older SoCs without qcom,ice > remain valid. > > Co-developed-by: Abel Vesa <[email protected]> > Signed-off-by: Abel Vesa <[email protected]> > Co-developed-by: Abhinaba Rakshit <[email protected]> > Signed-off-by: Abhinaba Rakshit <[email protected]> > Reviewed-by: Krzysztof Kozlowski <[email protected]> > Signed-off-by: Neeraj Soni <[email protected]> > Signed-off-by: Kuldeep Singh <[email protected]> Applied for next, thanks! Kind regards Uffe > --- > .../devicetree/bindings/mmc/qcom,sdhci-msm.yaml | 95 +++++++++++++++------- > 1 file changed, 67 insertions(+), 28 deletions(-) > > diff --git a/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml > index bd558a11b792..b3fcc1673c10 100644 > --- a/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml > +++ b/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml > @@ -145,6 +145,11 @@ properties: > $ref: /schemas/types.yaml#/definitions/uint32 > description: platform specific settings for DLL_CONFIG reg. > > + qcom,ice: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + phandle to the Inline Crypto Engine (ICE) hardware block for this controller. > + > iommus: > minItems: 1 > maxItems: 8 > @@ -198,35 +203,69 @@ allOf: > enum: > - qcom,sdhci-msm-v4 > then: > - properties: > - reg: > - minItems: 2 > - items: > - - description: Host controller register map > - - description: SD Core register map > - - description: CQE register map > - - description: Inline Crypto Engine register map > - reg-names: > - minItems: 2 > - items: > - - const: hc > - - const: core > - - const: cqhci > - - const: ice > + if: > + required: > + - qcom,ice > + then: > + properties: > + reg: > + minItems: 2 > + items: > + - description: Host controller register map > + - description: SD Core register map > + - description: CQE register map > + reg-names: > + minItems: 2 > + items: > + - const: hc > + - const: core > + - const: cqhci > + else: > + properties: > + reg: > + minItems: 2 > + items: > + - description: Host controller register map > + - description: SD Core register map > + - description: CQE register map > + - description: Inline Crypto Engine register map > + reg-names: > + minItems: 2 > + items: > + - const: hc > + - const: core > + - const: cqhci > + - const: ice > else: > - properties: > - reg: > - minItems: 1 > - items: > - - description: Host controller register map > - - description: CQE register map > - - description: Inline Crypto Engine register map > - reg-names: > - minItems: 1 > - items: > - - const: hc > - - const: cqhci > - - const: ice > + if: > + required: > + - qcom,ice > + then: > + properties: > + reg: > + minItems: 1 > + items: > + - description: Host controller register map > + - description: CQE register map > + reg-names: > + minItems: 1 > + items: > + - const: hc > + - const: cqhci > + else: > + properties: > + reg: > + minItems: 1 > + items: > + - description: Host controller register map > + - description: CQE register map > + - description: Inline Crypto Engine register map > + reg-names: > + minItems: 1 > + items: > + - const: hc > + - const: cqhci > + - const: ice > > unevaluatedProperties: false > > > -- > 2.34.1 >