RE: [PATCH v20 00/12] Add Renesas RZ/G3L SD/eMMC support

Hi All,

> -----Original Message-----
> From: Biju <[email protected]>
> Sent: 13 July 2026 18:52
> Subject: [PATCH v20 00/12] Add Renesas RZ/G3L SD/eMMC support
> 
> From: Biju Das <[email protected]>
> 
> Hi All,
> 
> RZ/G3L SoC has:
> 
> Channel 0 supports SD and eMMC (including HS400/HS400ES).
> Channel 1 supports SD and eMMC (except for HS400).
> Channel 2 supports SD.
> 
> The SoC supports a maximum frequency of 150 MHz. The SD0 interface does not support IOVS and PWEN in the
> SDHI register (no internal regulator), unlike SD1 and SD2. It has an internal divider for all modes
> except HS400.
> It also has a 2048-bit divider compared to 512 on others. Moreover RZ/G3L supports HS400 enhanced strobe
> mode.

Most of the issues reported buy sashiko [1] are false positive
except the one pointed out by sashiko and Geert's testing results[2].

Please find the logs [3]

If there are no other comments, I planned to send the fix in v21 fixing the issue
with divider mask in of_data for RZ/G3L and non RZ/G3L SoCs:

clk = clk & host->pdata->clk_ctl_div_mask;

where,
GENMASK(7,0) --> For Non-RZ/G3L and  
GENMASK(9,0) --> For RZ/G3L

[1] https://sashiko.dev/#/patchset/20260713175159.138334-1-biju.das.jz%40bp.renesas.com

[2] https://lore.kernel.org/all/CAMuHMdXQDWJGxuU04PEo2bJgHJF5F+0=HXqKzthKhKSR6dg0Tg@mail.gmail.com/

[3]
root@smarc-rzg3l:~# mount -t auto /dev/mmcblk0p
mmcblk0p1  mmcblk0p2
root@smarc-rzg3l:~# mount -t auto /dev/mmcblk0p2 /mnt/
[  712.973996] EXT4-fs (mmcblk0p2): recovery complete
[  712.980081] EXT4-fs (mmcblk0p2): mounted filesystem 3a87d114-78ab-4be0-8fac-d055b25f4bd0 r/w with ordered data mode. Quota mode: none.
root@smarc-rzg3l:~# mount -t auto /dev/mmcblk1p1 /media/
[  725.035107] EXT4-fs (mmcblk1p1): recovery complete
[  725.041088] EXT4-fs (mmcblk1p1): mounted filesystem 2371cfa6-6402-4f3d-bbfc-84412835fa12 r/w with ordered data mode. Quota mode: none.
root@smarc-rzg3l:~# echo "MNT" > /mnt/1.txt
root@smarc-rzg3l:~# echo "MEDIA" > /media/1.txt
root@smarc-rzg3l:~# cat /sys/kernel/debug/mmc*/ios
clock:          150000000 Hz
actual clock:   8 Hz
vdd:            21 (3.3 ~ 3.4 V)
bus mode:       2 (push-pull)
chip select:    0 (don't care)
power mode:     2 (on)
bus width:      3 (8 bits)
timing spec:    10 (mmc HS400 enhanced strobe)
signal voltage: 1 (1.80 V)
driver type:    1 (driver type A)
clock:          150000000 Hz
actual clock:   150000000 Hz
vdd:            21 (3.3 ~ 3.4 V)
bus mode:       2 (push-pull)
chip select:    0 (don't care)
power mode:     2 (on)
bus width:      2 (4 bits)
timing spec:    6 (sd uhs SDR104)
signal voltage: 1 (1.80 V)
driver type:    0 (driver type B)
root@smarc-rzg3l:~# echo mem > /sys/power/state
[  814.141037] PM: suspend entry (deep)
[  814.154238] Filesystems sync: 0.008 seconds
[  814.165291] Freezing user space processes
[  814.175088] Freezing user space processes completed (elapsed 0.003 seconds)
[  814.182128] OOM killer disabled.
[  814.185452] Freezing remaining freezable tasks
[  815.162014] Freezing remaining freezable tasks completed (elapsed 0.972 seconds)
[  815.169895] printk: Suspending console(s) (use no_console_suspend to debug)
NOTICE:  BL2: v2.10.5(release):2.10.5/rzg3l_1.0.1_rc2
NOTICE:  BL2: Built : 09:19:29, Jun 16 2026
INFO:    BL2: Doing platform setup
INFO:    Configuring TrustZone Controller
INFO:    Total 3 regions set.
INFO:    Configuring TrustZone Controller
INFO:    Total 1 regions set.
INFO:    Configuring TrustZone Controller
INFO:    Total 1 regions set.
INFO:    Loading image id=39 at address 0x44428
INFO:    Image id=39 loaded: 0x44428 - 0x45428
INFO:    DDR: Retention Exit (Rev. 02.05)
NOTICE:  BL2: SYS_LSI_MODE: 0x12061
NOTICE:  BL2: SYS_LSI_DEVID: 0x87d9447
INFO:    BL2: Skip loading image id 3
INFO:    BL2: Skip loading image id 5
NOTICE:  BL2: Booting BL31
INFO:    Entry point address = 0x44000000
INFO:    SPSR = 0x3cd
[  815.219726] renesas-gbeth 11c30000.ethernet end0: Link is Down
[  815.223525] Disabling non-boot CPUs ...
[  815.225846] psci: CPU3 killed (polled 0 ms)
[  815.229727] psci: CPU2 killed (polled 0 ms)
[  815.233693] psci: CPU1 killed (polled 0 ms)
[  815.235466] Enabling non-boot CPUs ...
[  815.235737] Detected VIPT I-cache on CPU1
[  815.235797] GICv3: CPU1: found redistributor 100 region 0:0x0000000012460000
[  815.235846] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
[  815.236888] CPU1 is up
[  815.237039] Detected VIPT I-cache on CPU2
[  815.237075] GICv3: CPU2: found redistributor 200 region 0:0x0000000012480000
[  815.237109] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
[  815.237997] CPU2 is up
[  815.238151] Detected VIPT I-cache on CPU3
[  815.238188] GICv3: CPU3: found redistributor 300 region 0:0x00000000124a0000
[  815.238221] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
[  815.240113] CPU3 is up
[  815.251088] dwmac4: Master AXI performs fixed burst length
[  815.251135] renesas-gbeth 11c30000.ethernet end0: No Safety Features support found
[  815.251179] renesas-gbeth 11c30000.ethernet end0: IEEE 1588-2008 Advanced Timestamp supported
[  815.253278] renesas-gbeth 11c30000.ethernet end0: configuring for phy/rgmii-id link mode
[  815.270272] dwmac4: Master AXI performs fixed burst length
[  815.270302] renesas-gbeth 11c40000.ethernet end1: No Safety Features support found
[  815.270335] renesas-gbeth 11c40000.ethernet end1: IEEE 1588-2008 Advanced Timestamp supported
[  815.272427] renesas-gbeth 11c40000.ethernet end1: configuring for phy/rgmii-id link mode
[  815.444098] OOM killer enabled.
[  815.447249] Restarting tasks: Starting
[  815.452666] Restarting tasks: Done
[  815.456345] random: crng reseeded on system resumption
[  815.461744] PM: suspend exit
[  817.842801] renesas-gbeth 11c30000.ethernet end0: Link is Up - 1Gbps/Full - flow control rx/tx
root@smarc-rzg3l:~# cat /mnt/1.txt
MNT
root@smarc-rzg3l:~# cat /media/1.txt
MEDIA
root@smarc-rzg3l:~# cat /sys/kernel/debug/mmc*/ios
clock:          150000000 Hz
actual clock:   8 Hz
vdd:            21 (3.3 ~ 3.4 V)
bus mode:       2 (push-pull)
chip select:    0 (don't care)
power mode:     2 (on)
bus width:      3 (8 bits)
timing spec:    10 (mmc HS400 enhanced strobe)
signal voltage: 1 (1.80 V)
driver type:    1 (driver type A)
clock:          150000000 Hz
actual clock:   150000000 Hz
vdd:            21 (3.3 ~ 3.4 V)
bus mode:       2 (push-pull)
chip select:    0 (don't care)
power mode:     2 (on)
bus width:      2 (4 bits)
timing spec:    6 (sd uhs SDR104)
signal voltage: 1 (1.80 V)
driver type:    0 (driver type B)
root@smarc-rzg3l:~#

Cheers,
Biju
> 
> v19->v20:
>  * Replaced the check mmd->clk_mask with mmc_data->clk_mask and moved
>    the code after assignment of variable mmd, this ensures assigning
>    the default values for non-DT platforms and DT platforms with no
>    device data.
>  * Replaced the check mmd->max_divider with mmc_data->max_divider and
>    moved the code after assignment of variable mmd, this ensures
>    assigning the default values for non-DT platforms and DT platforms with
>    no device data.
>  * Fixed the ordering of resets in suspend/resume paths.
>  * Added bitfield.h header file.
>  * Reworked on renesas_sdhi_set_clock() to handle the 11-bit divider
>    case and the 32-bit register write.
>  * Updated resume() with scoped PM runtime call.
>  * SD_CLK_CTRL clk enable turned off before updating SCC_CKSEL_DTSEL
>    register.

> v18->v19:
>  * Updated commit description for patch#1,#2,#6,#8,#11 and #12
>  * Updated clock and reset description with AXI master and AXI slave
>  * Added else condition for reset and reset-names.
>  * Renamed aclk->aclkm and reordered the axi clocks similar to resets.
>  * Retained the tag got binding patch as the changes are trivial.
>  * Fixed the clk_mask for non-DT platforms.
>  * Fixed max-divider setting for non-DT platforms.
>  * Replaced the magic number '9' with ilog2 function in
>    renesas_sdhi_clk_enable().
>  * Dropped divider variable from struct renesas_sdhi.
>  * Updated renesas_sdhi_clk_update() to return rate for HS400 mode
>    and non HS400 mode(uses 1/2 internal divider).
>  * Updated handling for clk divider.
>  * Renamed TMIO_MMC_HWADJ2->TMIO_MMC_HWADJ to make it generic for
>    hardware tuning delays
>  * Dropped duplicate SH_MOBILE_SDHI_SCC_TMPPORT2 macro
>  * Updated suspend/resume with scoped runtime calls in suspend.
>  * Fixed extra space in HS400MODE2 comment block.
>  * Updated the comment HS400mode2->HS400MODE2.
>  * Dropped the updation of clk handling as it is taken care in
>    previous patches.
>  * HS400ES support is enabled based on of_data.
>  * Fixed the space in HS400ES comment block.
> 
> v17->v18:
>  * Collected tag
>  * Merged patch #4 and #5 and updated commit description
>  * Annotated the empty sentinel entries in the OF match tables with a
>    "Sentinel." comment for clarity.
>  * Retained the tag as it is a trivial cleanup.
>  * New patches drop struct renesas_sdhi_hw_info, instead using
>    renesas_sdhi_of_data and tmio_mmc_data.
>  * Dropped clk, pinctrl, SoC, and board dtsi from this patch series;
>    will send later.
> v1->v17:
>  * Collected tag for binding patch.
>  * Resending the series as there is an issue with patch threading from
>    patch #14.
> 
> Biju Das (12):
>   dt-bindings: mmc: renesas,sdhi: Document RZ/G3L (r9a08g046) SoC
>   mmc: renesas_sdhi: Clean up whitespace and add OF table sentinels
>   mmc: renesas_sdhi: Add clk_mask field to support flexible clock
>     divider widths
>   mmc: renesas_sdhi: Add max_divider field to support SoC-specific clock
>     ranges
>   mmc: renesas_sdhi: Add tuning delay support for RZ/G2L
>   mmc: renesas_sdhi: Add TMIO_MMC_INTERNAL_DIVIDER flag
>   mmc: renesas_sdhi: Add optional axis/axim reset controls
>   mmc: renesas_sdhi: Add RZ/G3L SDHI support
>   mmc: renesas_sdhi: Save and restore IOVS across suspend/resume
>   mmc: renesas_sdhi: Make HS400 OSEL bit configurable per SoC
>   mmc: renesas_sdhi: Add RZ/G3L HS400 support
>   mmc: renesas_sdhi: Add HS400 enhanced strobe support for RZ/G3L
> 
>  .../devicetree/bindings/mmc/renesas,sdhi.yaml | 108 +++++--
>  drivers/mmc/host/renesas_sdhi.h               |  11 +-
>  drivers/mmc/host/renesas_sdhi_core.c          | 274 ++++++++++++++----
>  drivers/mmc/host/renesas_sdhi_internal_dmac.c |  73 ++++-
>  drivers/mmc/host/renesas_sdhi_sys_dmac.c      |  12 +-
>  include/linux/platform_data/tmio.h            |  18 ++
>  6 files changed, 408 insertions(+), 88 deletions(-)
> 
> --
> 2.43.0