[PATCH v23 01/14] dt-bindings: mmc: renesas,sdhi: Document RZ/G3L (r9a08g046) SoC
Biju <[email protected]> Thu, 30 Jul 2026 12:31:39 +0100
| Newsgroups | org.kernel.vger.linux-mmc,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel,org.kernel.vger.linux-renesas-soc |
|---|---|
| Message-ID | <[email protected]> |
From: Biju Das <[email protected]> Document the RZ/G3L (r9a08g046) SDHI controller. The RZ/G3L SDHI controller is similar to RZ/G2L but has five clocks (core, clkh, cd, aclkm, aclks) and three resets (rst, axim, axis), so update the clocks/clock-names maximum to 5 and resets/reset-names maximum to 3. It has an internal divider for all modes except HS400, and a 2048-bit divider compared to 512 on others. Acked-by: Conor Dooley <[email protected]> Signed-off-by: Biju Das <[email protected]> --- v22->v23: * No change. v21->v22: * No change. v20->v21: * No change. v19->v20: * No change. v18->v19: * Updated commit description * Updated clock and reset description with AXI master and AXI slave * Added else condition for reset and reset-names. * Renamed aclk->aclkm and reordered the axi clocks similar to resets. * Retained the tag as the changes are trivial. v17->v18: * No change. v1->v17: * Collected tag. --- .../devicetree/bindings/mmc/renesas,sdhi.yaml | 108 +++++++++++++----- 1 file changed, 81 insertions(+), 27 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml index 4d66966ce290..6d229a41a4b5 100644 --- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml +++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml @@ -18,6 +18,7 @@ properties: - renesas,sdhi-r7s9210 # SH-Mobile AG5 - renesas,sdhi-r8a73a4 # R-Mobile APE6 - renesas,sdhi-r8a7740 # R-Mobile A1 + - renesas,sdhi-r9a08g046 # RZ/G3L - renesas,sdhi-r9a09g057 # RZ/V2H(P) - renesas,sdhi-sh73a0 # R-Mobile APE6 - items: @@ -86,11 +87,11 @@ properties: clocks: minItems: 1 - maxItems: 4 + maxItems: 5 clock-names: minItems: 1 - maxItems: 4 + maxItems: 5 dmas: minItems: 4 @@ -116,7 +117,12 @@ properties: maxItems: 1 resets: - maxItems: 1 + minItems: 1 + maxItems: 3 + + reset-names: + minItems: 1 + maxItems: 3 pinctrl-0: minItems: 1 @@ -155,60 +161,106 @@ allOf: properties: compatible: contains: - enum: - - renesas,sdhi-r9a09g057 - - renesas,rzg2l-sdhi + const: renesas,sdhi-r9a08g046 then: properties: clocks: items: - description: IMCLK, SDHI channel main clock1. - description: CLK_HS, SDHI channel High speed clock which operates - 4 times that of SDHI channel main clock1. + 2 times that of SDHI channel main clock1. - description: IMCLK2, SDHI channel main clock2. When this clock is turned off, external SD card detection cannot be detected. - - description: ACLK, SDHI channel bus clock. + - description: IACLKM, SDHI channel AXI master bus clock. + - description: IACLKS, SDHI channel AXI slave bus clock. clock-names: items: - const: core - const: clkh - const: cd - - const: aclk + - const: aclkm + - const: aclks + resets: + items: + - description: rst, Core reset. + - description: axim, SDHI channel AXI master bus reset. + - description: axis, SDHI channel AXI slave bus reset. + reset-names: + items: + - const: rst + - const: axim + - const: axis required: - clock-names - resets + - reset-names else: + properties: + resets: + maxItems: 1 + reset-names: + maxItems: 1 if: properties: compatible: contains: enum: - - renesas,rcar-gen2-sdhi - - renesas,rcar-gen3-sdhi - - renesas,rcar-gen4-sdhi + - renesas,sdhi-r9a09g057 + - renesas,rzg2l-sdhi then: properties: clocks: - minItems: 1 - maxItems: 3 - clock-names: - minItems: 1 - uniqueItems: true items: - - const: core - - enum: [ clkh, cd ] - - const: cd - else: - properties: - clocks: - minItems: 1 - maxItems: 2 + - description: IMCLK, SDHI channel main clock1. + - description: CLK_HS, SDHI channel High speed clock which operates + 4 times that of SDHI channel main clock1. + - description: IMCLK2, SDHI channel main clock2. When this clock is + turned off, external SD card detection cannot be + detected. + - description: ACLK, SDHI channel bus clock. clock-names: - minItems: 1 items: - const: core + - const: clkh - const: cd + - const: aclk + resets: + maxItems: 1 + required: + - clock-names + - resets + else: + if: + properties: + compatible: + contains: + enum: + - renesas,rcar-gen2-sdhi + - renesas,rcar-gen3-sdhi + - renesas,rcar-gen4-sdhi + then: + properties: + clocks: + minItems: 1 + maxItems: 3 + clock-names: + minItems: 1 + uniqueItems: true + items: + - const: core + - enum: [ clkh, cd ] + - const: cd + else: + properties: + clocks: + minItems: 1 + maxItems: 2 + clock-names: + minItems: 1 + items: + - const: core + - const: cd - if: properties: @@ -247,7 +299,9 @@ allOf: properties: compatible: contains: - const: renesas,sdhi-r9a09g057 + enum: + - renesas,sdhi-r9a08g046 + - renesas,sdhi-r9a09g057 then: properties: vqmmc-regulator: -- 2.43.0