RE: [PATCH v23 10/14] mmc: renesas_sdhi: Add RZ/G3L SDHI support

Hi Geert,

Thanks for the feedback.

> -----Original Message-----
> From: Geert Uytterhoeven <[email protected]>
> Sent: 07 August 2026 14:28
> Subject: Re: [PATCH v23 10/14] mmc: renesas_sdhi: Add RZ/G3L SDHI support
> 
> Hi Biju,
> 
> On Thu, 30 Jul 2026 at 13:32, Biju <[email protected]> wrote:
> > From: Biju Das <[email protected]>
> >
> > RZ/G3L (r9a08g046) has an SDHI controller that differs from existing
> > platforms in clock divider width, a second HW adjustment register, and
> > an extra tuning register.
> >
> > Add TMIO_MMC_HWADJ to mark controllers with a second HWADJ2 register
> > (offset 0x010), programmed by renesas_sdhi_set_hw_adjustment_delay()
> > alongside TMPPORT2 (0x3FFF at 3.3V, 0xFF at 1.8V). Clear the new
> > HWADJ4 register (0x022) at tuning start when TMIO_MMC_INTERNAL_DIVIDER
> > is set.
> >
> > Update renesas_sdhi_set_clock() to write the clock control register
> > with a 32-bit access when max_divider isn't the default, moving bits
> > [9:8] of the clock value into bits [17:16] of the register — needed to
> > drive RZ/G3L's wider 11-bit divider field via the max_divider/
> > clk_div_mask support added earlier in this series.
> >
> > Add SDHI_VER_RZ_G3L_SDMMC (0xce10) and handle it in
> > renesas_sdhi_sdbuf_width(). Add of_data_rzg3l with RZ/G3L's wider
> > clk_mask, an 11-bit max_divider of 2048, a dedicated tap table, and
> > the relevant flags including TMIO_MMC_INTERNAL_DIVIDER and
> > TMIO_MMC_HWADJ. Wire it up via of_rzg3l_compatible (fixed_addr_mode
> > quirk) and register the "renesas,sdhi-r9a08g046" compatible string.
> >
> > Signed-off-by: Biju Das <[email protected]>
> > ---
> > v22->v23:
> >  * Updated tmio_mmc_reset() to handle 32 bit divider register in RZ/G3L.
> > v21->v22:
> >  * Updated commit description.
> >  * Added `clock &= ~GENMASK(9, 8)` to clear the divider mask bits in
> >    the register value.
> 
> Thanks for the update!
> 
> > --- a/drivers/mmc/host/renesas_sdhi_core.c
> > +++ b/drivers/mmc/host/renesas_sdhi_core.c
> 
> > @@ -253,7 +256,17 @@ static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
> >         if (clock != CLK_CTL_DIV_MASK)
> >                 host->mmc->actual_clock /= (1 << (ffs(clock) + 1));
> >
> > -       sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clock);
> > +       if (host->pdata->max_divider != SDHI_MAX_DIVIDER_DEFAULT) {
> > +               u64 tmp;
> > +
> > +               tmp = FIELD_GET(GENMASK(9, 8), clk);
> > +               clock |= FIELD_PREP(GENMASK(17, 16), tmp);
> > +               clock &= ~GENMASK(9, 8);
> 
> Add #defines for the magic bits?
SD_CLK_CTRL[7:0] (DIV0 to 7)
SD_CLK_CTRL[17:16] (DIV8 to 9)

These are the divider bits defined in the SD_CLK_CTRL register,

Will define this as SD_CLK_CTRL_HI_DIVIDER for GENMASK(17, 16)
and SD_CLK_CTRL_HI_DIVIDER_SRC_MASK for GENMASK(9, 8). The later
macro is temporary one for clk divider manipulation.

> We already have CLK_CTL_SCLKEN for BIT(8).

OK.

Cheers,
Biju

> 
> > +               sd_ctrl_write32(host, CTL_SD_CARD_CLK_CTL, clock);
> > +       } else {
> > +               sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clock);
> > +       }
> > +
> >         if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
> >                 usleep_range(10000, 11000);
> >
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
> 
> In personal conversations with technical people, I call myself a hacker. But when I'm talking to
> journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds