Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The `interrupts`, `interrupt-map`, and `iommu-map` properties are swapped between the `pcie0` and `pcie1` device tree nodes.
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--- Patch [1]: [PATCH v5 1/3] arm64: dts: qcom: eliza: Add PCIe PHY and controller nodes ---
commit da247ac5c4684b405ce8a69950ea44574f919a8d
Author: Krishna Chaitanya Chundru <[email protected]>
arm64: dts: qcom: eliza: Add PCIe PHY and controller nodes
Eliza supports two PCIe instances: one 8GT/s x1 (PCIe0) and one 8GT/s x2
(PCIe1). This commit adds PCIe controller and PHY nodes for both instances,
and updates the GCC clock references to use the new PHY nodes.
> diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi
> index 357e8066c1768..31835a5828834 100644
> --- a/arch/arm64/boot/dts/qcom/eliza.dtsi
> +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi
[ ... ]
> + pcie0: pcie@1c00000 {
[ ... ]
> + interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
[ ... ]
> + iommu-map = <0 &apps_smmu 0x1480 0x1>,
> + <0x100 &apps_smmu 0x1481 0x1>;
> +
> + interrupt-map = <0 0 0 1 &intc 0 0 0 564 IRQ_TYPE_LEVEL_HIGH>,
[Severity: High]
Are the interrupts, interrupt-map, and iommu-map properties swapped between
pcie0 and pcie1?
Here pcie0 (at hardware base 0x01c00000) is assigned interrupts 376+,
interrupt-map 564+, and IOMMU stream ID 0x1480, which are typically
hardwired to the pcie1 block.
[ ... ]
> + pcie1: pcie@1c08000 {
[ ... ]
> + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
[ ... ]
> + iommu-map = <0 &apps_smmu 0x1400 0x1>,
> + <0x100 &apps_smmu 0x1401 0x1>;
> +
> + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
[Severity: High]
Similarly, pcie1 (at hardware base 0x01c08000) is assigned interrupts 141+,
interrupt-map 149+, and IOMMU stream ID 0x1400.
Does this cause SMMU translation faults during DMA and dropped interrupts for
both PCIe controllers by assigning pcie0's hardware mappings to pcie1?
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Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=1
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