Re: [PATCH] PCI: Fix Intel Xeon 6 x2 quirk collateral damage on adjacent x4 endpoints

On Wed, Jul 29, 2026 at 10:45:08AM -0400, Rick Warner wrote:
> commit a22250fe933d ("PCI: Add Extended Tag + MRRS quirk for Xeon 6")
> introduced a traffic mitigation quirk for Intel Xeon 6 root ports that
> negotiate down to an x2 lane width. However, that patch manipulated host
> bridge properties globally via 'bridge->no_ext_tags = 1' and by hooking
> 'bridge->enable_device'.
> 
> Because multiple unrelated root ports can reside under the exact same
> global pci_host_bridge domain structure, this overly aggressive mitigation
> causes severe collateral damage. When a low-speed or bifurcated secondary
> device (such as an onboard ASMedia SATA controller or BMC graphics link)
> matches the x2 condition, the kernel strips away Extended Tags and forces
> a 128B MRRS restriction across that ENTIRE host bridge. This instantly
> breaks or starves adjacent high-performance, unrelated x4 endpoints
> (such as NVMe drives), resulting in controller timeouts, initialization
> failures, and missing drives at boot.
> 
> Fix this by refactoring the quirk logic to be completely per-device and
> downstream-isolated. Remove the broad host bridge structure assignments
> entirely. Instead, convert the hook to an explicit
> 'DECLARE_PCI_FIXUP_FINAL' sweep. When an x2 bifurcated root port is
> discovered, leverage 'pci_walk_bus()' to step down only that specific root
> port's subordinate tree, manually clearing 'PCI_EXP_DEVCTL_EXT_TAG' and
> 'PCI_EXP_DEVCTL_READRQ' directly in the endpoint Device Control
> configuration registers.

One problem I see with this approach is that it won't work for hotplugged
devices below a bifurcated Root Port:  You're only adjusting Extended Tags
and MRRS once on enumeration of the Root Ports, leaving devices that are
hotplugged later at incorrect settings.

But perhaps you could simply amend limit_mrrs_to_128() to walk up to the
Root Port, check whether it is bifurcated, and bail out if it's not?

Thanks,

Lukas