[PATCH v2 1/2] PCI: dwc: ep: Flush the cached MSI address before unmap
Niklas Cassel <[email protected]> Thu, 30 Jul 2026 15:31:25 +0200
| Newsgroups | org.kernel.vger.linux-pci |
|---|---|
| Message-ID | <[email protected]> |
While we do a flush before unmap in dw_pcie_ep_raise_msix_irq(),
see commit c22533c66cca ("PCI: dwc: ep: Flush MSI-X write before unmapping
its ATU entry"), we do not do a flush before unmap in
dw_pcie_ep_raise_msi_irq(), if the cached MSI target address changed.
Fix this by doing a flush before unmap.
Reported-by: Sashiko <[email protected]>
Link: https://lore.kernel.org/linux-pci/[email protected]/
Fixes: 468711a40d5d ("PCI: dwc: ep: Refresh MSI Message Address cache on change")
Signed-off-by: Niklas Cassel <[email protected]>
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 3 +++
drivers/pci/controller/dwc/pcie-designware.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 7d2794945704..3128e7ae8c5f 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -1032,6 +1032,8 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
* there is no unified way to check if we have operations in
* flight, thus we don't know if we should WARN() or not.
*/
+ /* flush posted write before unmap */
+ readl(ep->msi_mem + ep->msi_iatu_mapped_offset);
dw_pcie_ep_unmap_addr(epc, func_no, 0, ep->msi_mem_phys);
ep->msi_iatu_mapped = false;
}
@@ -1044,6 +1046,7 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
return ret;
ep->msi_iatu_mapped = true;
+ ep->msi_iatu_mapped_offset = offset;
ep->msi_msg_addr = msg_addr;
ep->msi_map_size = map_size;
}
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index de4b245b1758..1d2139474157 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -518,6 +518,7 @@ struct dw_pcie_ep {
/* MSI outbound iATU state */
bool msi_iatu_mapped;
+ size_t msi_iatu_mapped_offset;
u64 msi_msg_addr;
size_t msi_map_size;
};
--
2.55.0