[PCI] AMD RX780/RD790 root port and RX 6600 upstream bridge train at Gen2 x2; RX 570 reaches Gen2 x8 in the same slot

Hello,

I am requesting guidance on a reproducible PCIe link-width interoperability
problem involving an old AMD RX780/RD790 root port and an AMD Radeon RX 6600.
This is not yet claimed to be a Linux regression: the evidence currently
localizes the problem to link training on one external hop.

Hardware
========

Motherboard: MSI 870-C45 (MS-7599)
Chipset: AMD 770 / SB710; GFX root port identified as RX780/RD790
BIOS: AMI V1.15, 2011-03-04
CPU: AMD Phenom II X6 1055T
GPU under test: ASRock Radeon RX 6600, Navi 23 [1002:73ff]
Control GPU: Radeon RX 570, Ellesmere [1002:67df]

Linux environments tested
=========================

* Gentoo LiveCD, Linux 6.18.38, with amdgpu not loaded or bound
* gentoo-sources 6.18.39 custom kernel
* Gentoo distribution binary kernel 6.18.39

RX 6600 topology and observed links
===================================

00:02.0 [1002:5978] AMD RX780/RD790 root port
  LnkCap: 5.0 GT/s, Width x16
  LnkSta: 5.0 GT/s, Width x2

01:00.0 [1002:1478] AMD upstream port of the GPU PCIe switch
  LnkCap: 16.0 GT/s, Width x8
  LnkSta: 5.0 GT/s, Width x2

02:00.0 [1002:1479] AMD downstream port
  LnkCap/LnkSta: 16.0 GT/s, Width x16

03:00.0 [1002:73ff] Navi 23 GPU endpoint
  LnkCap/LnkSta: 16.0 GT/s, Width x16

Thus the affected external hop is 00:02.0 <-> 01:00.0. Its common maximum is
Gen2 x8. The internal 02:00.0 <-> 03:00.0 x16 link is healthy and must not be
confused with the external card interface.

Control result with RX 570
==========================

Using the same motherboard, physical slot, Gentoo LiveCD and Linux 6.18.38:

00:02.0 [1002:5978]
  LnkCap: 5.0 GT/s, Width x16
  LnkSta: 5.0 GT/s, Width x8

01:00.0 RX 570 [1002:67df]
  LnkCap: 8.0 GT/s, Width x16
  LnkSta: 5.0 GT/s, Width x8

This demonstrates that the board/root port/slot and this Linux environment can
operate at least eight lanes. The reduced width follows the RX 6600 or the
specific RX780/RD790 <-> [1002:1478] pairing.

Early and repeated observations
===============================

* pci=earlydump on the custom kernel captured root-port LnkSta 0xf022,
  corresponding to Gen2 x2, before normal driver initialization.
* Current root-port LnkSta remained Gen2 x2.
* The result was stable for 72/72 samples after a cold boot and 12/12 samples
  after complete power removal and reseating.
* No AER errors were reported, but this does not prove that unused lanes are
  electrically functional.
* The RX 6600 produces video and remains stable at x2.

Experiments already completed without improvement
=================================================

* normal PCIe link retrain;
* an early kernel retrain before amdgpu;
* Gen1 -> Gen2 target-speed cycle;
* Secondary Bus Reset;
* amdgpu PCIe DPM state changes.

Each completed with the external hop still at x2. A Link Disable experiment
hung during early PCI enumeration and must not be repeated.

AMD RD790 indirect register observation
=======================================

PCIEIND_P_A2 = 0x00000226

Decoded from related AMD documentation/source material:

* intended/target width code: 6 (x16 at the root port);
* trained/current width code: 2 (x2);
* renegotiation support: 1;
* renegotiation enable: 0;
* upconfigure support: 0.

No width value was written. A forced vendor-register write is intentionally
not being attempted because current width is below intended width and the
platform does not report upconfigure support.

Questions
=========

1. Is there a known interoperability erratum or quirk for the AMD
   RX780/RD790 [1002:5978] root port paired with AMD [1002:1478]?
2. Is there any upstream-supported read-only diagnostic that can identify why
   lanes 2-7 fail to become active during initial training?
3. Would a PCI quirk be appropriate here, or does the early Gen2 x2 state make
   this a firmware/electrical issue outside Linux control?
4. Which exact config-space dumps or traces would maintainers like next?

I can provide full lspci -vvxxx output, earlydump/current config bytes, dmesg,
kernel configurations, and the existing experiment reports. I will not repeat
Link Disable, force a vendor width register, or run additional PCI writes
without a reviewed procedure.

Thank you.