Re: [PATCH v5] PCI: imx6: Update MPLLB bandwidth to improve i.MX95 Gen3 PCIe stability

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Two consecutive `regmap_update_bits()` calls on the same register `IMX95_PCIE_PHY_REG_ADDR` create a transient invalid hardware state.
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--- Patch [1]: [PATCH v5] PCI: imx6: Update MPLLB bandwidth to improve i.MX95 Gen3 PCIe stability ---
commit 4d9e90f9649b735da05c82cf73f9ef235bcf11f8
Author: Richard Zhu <[email protected]>

PCI: imx6: Update MPLLB bandwidth to improve i.MX95 Gen3 PCIe stability

This commit updates the MPLLB bandwidth override values to improve PCIe stability
on i.MX95 across voltage and temperature variations. It implements a PHY register
write helper and configures the bandwidth parameters during initialization.

> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 98e1db751132a..ad7efae23cc50 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c

[ ... ]

> @@ -269,6 +280,15 @@ static int imx95_pcie_select_ref_clk_src(struct imx_pcie *imx_pcie)
>  	return 0;
>  }
>  
> +static void imx95_pcie_phy_write(struct imx_pcie *imx_pcie, int addr, u16 data)
> +{
> +	regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_PHY_REG_ADDR,
> +			   IMX95_PCIE_PHY_REG_EN, IMX95_PCIE_PHY_REG_EN);
> +	regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_PHY_REG_ADDR,
> +			   IMX95_PCIE_PHY_REG_ADDR_MASK, addr);

[Severity: Medium]
Could these two consecutive updates on IMX95_PCIE_PHY_REG_ADDR create a
transient invalid hardware state?

Setting IMX95_PCIE_PHY_REG_EN first and IMX95_PCIE_PHY_REG_ADDR_MASK second
might expose an intermediate state where the PHY evaluates the address while EN
is asserted, but the address bits contain a previous value. This could
result in a spurious access to the old address.

Can these operations be combined into a single regmap_update_bits() call to
avoid this?

> +	regmap_write(imx_pcie->iomuxc_gpr, IMX95_PCIE_PHY_REG_DATA, data);
> +}
> +

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Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=1