Re: [PATCH v2] PCI: Fix 32-bit config write in Intel RP MPC ACS quirk
Manivannan Sadhasivam <[email protected]>
| Newsgroups | org.kernel.vger.linux-pci,org.kernel.vger.linux-kernel |
|---|---|
| Message-ID | <eph6rxwk6iyjze2vfzlqxsiisknc7baoq5f5hljpxbvixf6sah@zdi47j7zt3zy> |
On Thu, Jul 23, 2026 at 10:42:03PM +0530, Mohamad Raizudeen wrote:
> The pci_quirk_enable_intel_rp_mpc_acs() reads a 32 bit DWORD from the
> MPC register, sets bit 26 (INTEL_MPC_REG_IRBNCE), but it writes it back
> using pci_write_config_word().
>
> Because bit 26 resides in the upper 16 bits of the 32 bit register, a 16
> bit write to offset 0xd8 completely drops the newly set bit. The quirk
> logs that it is enabling IRBNCE, but the hardware never actually
> receives the command.
>
> Fix this by using pci_write_config_dword() to ensure the full 32 bit
> value is written back to the hardware.
>
> Fixes: d99321b63b1f ("PCI: Enable quirks for PCIe ACS on Intel PCH root ports")
> Signed-off-by: Mohamad Raizudeen <[email protected]>
Cc: [email protected]
Reviewed-by: Manivannan Sadhasivam <[email protected]>
- Mani
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