Re: [PATCH] PCI: aspeed: fix clk and phy leak in aspeed_pcie_port_init error paths
| Newsgroups | org.kernel.vger.linux-pci |
|---|---|
| Message-ID | <[email protected]> |
> aspeed_pcie_port_init() calls clk_prepare_enable() to enable the port
> clock, but if phy_init() or phy_set_mode_ext() fails afterwards, the
> function returns without calling clk_disable_unprepare(), leaking the
> clock reference on every probe failure. Additionally, when
> phy_set_mode_ext() fails, phy_init() has already succeeded, so
> phy_exit() is also missing, leaking the phy reference.
>
> Add the matching clk_disable_unprepare() to both error paths, and
> phy_exit() to the phy_set_mode_ext() failure path, mirroring the
> cleanup pattern in pci-aardvark.
>
> Compile-tested with gcc on arm64 defconfig using COMPILE_TEST; no
> hardware available for runtime testing.
>
> Fixes: 9aa0cb68fcc1 ("PCI: aspeed: Add ASPEED PCIe RC driver")
> Cc: [email protected]
> Assisted-by: Claude:claude-opus-5
> Signed-off-by: Liu Zhenlong <[email protected]>
Sashiko has reviewed this patch and found no issues. It looks great!
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Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=1