[PATCH v2 1/2] PCI: Add MMIO Capabilities Register Block definitions
penn <[email protected]>
| Newsgroups | org.kernel.vger.linux-pci,org.kernel.vger.linux-cxl,org.kernel.vger.linux-kernel |
|---|---|
| Message-ID | <[email protected]> |
From: Penn <[email protected]> PCIe r7.0 sec 6.35 defines the MMIO Capabilities Register Block (MCAP). It consists of an array header followed by capability headers that identify the version, location, size, and vendor of each MMIO capability. Define the MCAP array-header and capability-header registers and their fields. These definitions allow subsystem drivers to use the Vendor ID along with the Capability ID when capabilities from multiple vendors share the same MCAP. Signed-off-by: Penn <[email protected]> --- Changes in v2: - Update the MCAP specification citation to PCIe r7.0 sec 6.35. - Document that capability header indices are one-based. include/uapi/linux/pci_regs.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 14f634ab9350..4dd22cde9e71 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -1338,6 +1338,28 @@ #define PCI_IDE_SEL_ADDR_3(x) (28 + (x) * PCI_IDE_SEL_ADDR_BLOCK_SIZE) #define PCI_IDE_SEL_BLOCK_SIZE(nr_assoc) (20 + PCI_IDE_SEL_ADDR_BLOCK_SIZE * (nr_assoc)) +/* PCIe r7.0, sec 6.35: MMIO Capabilities Register Block (MCAP) */ +#define PCI_MCAP_ARRAY_1 0x00 +#define PCI_MCAP_ARRAY_ID __GENMASK(15, 0) +#define PCI_MCAP_ARRAY_VERSION __GENMASK(23, 16) +#define PCI_MCAP_ARRAY_TYPE __GENMASK(27, 24) +#define PCI_MCAP_ARRAY_TYPE_CLASS_CODE 0x0 +#define PCI_MCAP_ARRAY_2 0x04 +#define PCI_MCAP_ARRAY_COUNT __GENMASK(15, 0) + +/* Capability header indices are one-based. */ +#define PCI_MCAP_HDR_SIZEOF 0x10 +#define PCI_MCAP_HDR_BASE(n) ((n) * PCI_MCAP_HDR_SIZEOF) +#define PCI_MCAP_HDR_REG_1 0x00 +#define PCI_MCAP_CAP_ID __GENMASK(15, 0) +#define PCI_MCAP_CAP_VERSION __GENMASK(23, 16) +#define PCI_MCAP_HDR_REG_2 0x04 +#define PCI_MCAP_HDR_OFFSET __GENMASK(31, 0) +#define PCI_MCAP_HDR_REG_3 0x08 +#define PCI_MCAP_HDR_LENGTH __GENMASK(31, 0) +#define PCI_MCAP_HDR_REG_4 0x0c +#define PCI_MCAP_HDR_VENDOR_ID __GENMASK(15, 0) + /* * Compute Express Link (CXL r4.0, sec 8.1) * -- 2.43.0