Re: [PATCH] PCI/ASPM: Clear L1SS capability when L1 latency is unacceptable

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Hardware State Desynchronization: Clearing PCIE_LINK_STATE_L1SS from `link->aspm_capable` prevents the kernel from properly disabling L1 PM Substates in hardware configuration registers.
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--- Patch [1]: [PATCH] PCI/ASPM: Clear L1SS capability when L1 latency is unacceptable ---
commit b94fabc7c75525f540a542b9992482d82ee2ac83
Author: Aniket Maurya <[email protected]>

PCI/ASPM: Clear L1SS capability when L1 latency is unacceptable

This commit clears PCIE_LINK_STATE_L1SS from link->aspm_capable when L1
exit latency is unacceptable. This prevents L1SS sysfs control files from
being exposed and avoids invoking pcie_config_aspm_l1ss() unnecessarily.

> diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
> index 172783e7f519a..38eb7b1e23774 100644
> --- a/drivers/pci/pcie/aspm.c
> +++ b/drivers/pci/pcie/aspm.c
> @@ -666,7 +666,8 @@ static void pcie_aspm_check_latency(struct pci_dev *endpoint)
>  		latency = max_t(u32, latency_up_l1, latency_dw_l1);
>  		if ((link->aspm_capable & PCIE_LINK_STATE_L1) &&
>  		    (latency + l1_switch_latency > acceptable_l1))
> -			link->aspm_capable &= ~PCIE_LINK_STATE_L1;
> +			link->aspm_capable &= ~(PCIE_LINK_STATE_L1 |
> +						PCIE_LINK_STATE_L1SS);

[Severity: High]
Does clearing PCIE_LINK_STATE_L1SS here prevent the kernel from disabling
L1 PM Substates in the hardware configuration registers if the BIOS left
them enabled?

When pcie_config_aspm_link() runs later to apply the state, it checks this
exact capability before performing the cleanup:

pcie_config_aspm_link() {
    ...
    if (link->aspm_capable & PCIE_LINK_STATE_L1SS)
        pcie_config_aspm_l1ss(link, state);
    ...
}

Because the capability was stripped earlier in pcie_aspm_check_latency(),
this condition evaluates to false. Will this bypass the hardware cleanup
routine, leaving stale BIOS configurations active and causing L1 to be
disabled while L1SS remains enabled in hardware?

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Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=1