Re: [PATCH v8 0/3] perf: marvell: Add CN20K DDR PMU support

On Mon, 01 Jun 2026 13:03:15 +0530, Geetha sowjanya wrote:
> This series adds support for the DDR Performance Monitoring Unit (PMU)
> present in Marvell CN20K SoCs.
> 
> The DDR PMU is part of the DRAM Subsystem (DSS) and provides hardware
> counters to monitor DDR traffic and performance events. The block
> implements eight programmable counters and two fixed-function counters
> tracking DDR read and write activity, and is accessed via a dedicated
> MMIO region.
> 
> [...]

Applied to arm64 (for-next/perf), thanks!

[1/3] dt-bindings: perf: marvell: Add CN20K DDR PMU binding
      https://git.kernel.org/arm64/c/6e0aa591af99
[2/3] perf: marvell: Add CN20K DDR PMU support
      https://git.kernel.org/arm64/c/9b551a2446b2
[3/3] perf: marvell: Cancel CN10K DDR PMU hrtimer on device remove
      https://git.kernel.org/arm64/c/7dbcb0268d1e

Cheers,
-- 
Will

https://fixes.arm64.dev
https://next.arm64.dev
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