Re: [PATCH v1 1/2] perf: RISC-V: use BIT_ULL for u64 overflow masks

Paul Walmsley <[email protected]> Fri, 7 Aug 2026 18:46:35 -0600 (MDT)

Newsgroups	org.kernel.vger.linux-perf-users,org.infradead.lists.linux-arm-kernel,org.infradead.lists.linux-riscv,org.kernel.vger.linux-kernel
Message-ID	<[email protected]>

Hi,

On Fri, 7 Aug 2026, Xixin Liu wrote:

> Overflow status and restart masks are u64, but bits were built with
> BIT(). On RV32 that is an unsigned long shift, so indices >= 32 truncate
> or wrap and corrupt the mask.
> 
> Use BIT_ULL() for those u64 bitops.
> 
> Signed-off-by: Xixin Liu <[email protected]>

Thanks for the patch, but, same comments as on

  https://lore.kernel.org/linux-riscv/[email protected]/T/#m6fa97e46bde0d100fa0ec2854d47a57bd271c0b3


- Paul